參數(shù)資料
型號(hào): HYB18H256321BF-12
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
中文描述: 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.22 ns, PBGA136
封裝: GREEN, PLASTIC, TFBGA-136
文件頁數(shù): 34/41頁
文件大?。?/td> 1302K
代理商: HYB18H256321BF-12
HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
34
Data-in and Data Mask to WDQS Setup
Time
Data-in and Data Mask to WDQS Hold
Time
Data-in and DM input pulse width (each
input)
DQS input low pulse width
DQS input high pulse width
DQS Write Preamble Time
DQS Write Postamble Time
Write Recovery Time
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
Read Postamble
Data-out high impedance time from CLK
t
HZ
Data-out low impedance time from CLK
DQS edge to Clock edge skew
DQS edge to output data edge skew
Data hold skew factor
Data output hold time from DQS
Refresh/Power Down Timing
Refresh Period (8192 cycles)
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
Self Refresh Exit time
Power Down Exit time
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep Out timing
Rev. ID EMRS to DQ on timing
Rev. ID EMRS to DQ off timing
1) DLL on mode ( -10/-11/-12/-14
f
CK(Min
)= 400 MHz)
2) DLL on mode ( -10/-11/-12/-14
f
CK(Min
)= 400 MHz)
3)
t
HP
is the lesser of
t
CL
minimum and
t
CH
minimum actually applied to the device CLK, CLK inputs
4) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
5)
t
MRD
is defined from MRS to any other command then READ
6)
t
RASmax
is 8*
t
REF
7)
t
RCDWR(Min)
may not drop below 2
×
t
CK
t
DS
0.14
0.15
0.16
0.18
ns
t
DH
0.14
0.15
0.16
0.18
ns
t
DIPW
0.40
0.40
0.40
0.40
t
CK
t
DQSL
t
DQSH
t
WPRE
t
WPST
t
WR
0.40
0.40
0.75
0.75
13
1.25
1.25
0.40
0.40
0.75
0.75
13
1.25
1.25
0.40
0.40
0.75
0.75
12
1.25
1.25
0.40
0.40
0.75
0.75
10
1.25
1.25
t
CK
t
CK
t
CK
t
CK
t
CK
8)
t
AC
t
RPRE
t
RPST
-0.21 0.21
0.75
0.75
t
ACmin
t
ACmax
t
ACmin
t
ACmax
t
ACmin
t
ACmax
t
ACmin
t
ACmin
t
ACmax
t
ACmin
t
ACmax
t
ACmin
t
ACmax
t
ACmin
-0.21 0.21
-0.22 0.22
0.120 —
0.130 —
0.120 —
0.130 —
t
HP
t
QHS
-0.22 0.22
0.75
0.75
-0.22 0.22
0.75
0.75
–0.25 0.25
0.75
0.75
ns
t
CK
t
CK
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
t
ACmax
ns
t
ACmax
ns
t
LZ
t
DQSCK
t
DQSQ
t
QHS
t
QH
-0.22 0.22
–0.25 0.25
ns
0.140 —
0.140 —
0.160 ns
0.160 ns
11)
ns
t
REF
t
REFI
t
RFC
t
XSC
t
XPN
3.9
52.0
1000
7
32
3.9
52.0
1000
7
32
3.9
52.0
1000
7
32
3.9
52.0
1000
6
32
ms
μ
s
ns
t
CK
t
CK
t
ATS
t
ATH
t
KO
t
RIDon
t
RIDoff
10
10
10
20
20
10
10
10
20
20
10
10
10
20
20
10
10
10
20
20
ns
ns
ns
ns
ns
Parameter
CAS latency
Symbol Limit Values
Unit
Note
–10
–11
–12
–14
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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