參數(shù)資料
型號(hào)： HYB18H256321BF-12
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
中文描述： 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.22 ns, PBGA136
封裝： GREEN, PLASTIC, TFBGA-136
文件頁(yè)數(shù)： 11/41頁(yè)
文件大?。?/td> 1302K
代理商： HYB18H256321BF-12
HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
11
3
Functional Description
3.1
Mode Register Set Command (MRS)
FIGURE 2
Mode Register Set Command
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of
t
MRD
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
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