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參數(shù)資料
| 型號： | HY63V8400 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 512Kx8Bit CMOS FAST SRAM |
| 中文描述： | 512Kx8Bit的CMOS快速靜態(tài)存儲器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 108K |
| 代理商： | HY63V8400 |
HY63V8400 Series
Rev.02 / Jan.99
6
WRITE CYCLE 1(/OE Clocked)
ADDR
OE
CS
Data
Out
tWC
tDW
tOHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
WRITE CYCLE 2(/OE Low Fixed)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(7)
(8)
tOW
ADDR
CS
Data
Out
tWC
Notes(Write Cycle)
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going
high and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as
/CS or /WE going high.
5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high
impedance state.
7. D
OUT
is the same phase of latest written data in the write cycle.
8. D
OUT
is the read data of the new address.
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