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參數(shù)資料
| 型號(hào)： | HY5S6B6DSFP-BE |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4Banks x1M x 16bits Synchronous DRAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 9 ns, PBGA54 |
| 封裝： | 0.80 MM PITCH, LEAD FREE, FBGA-54 |
| 文件頁(yè)數(shù)： | 10/27頁(yè) |
| 文件大?。?/td> | 368K |
| 代理商： | HY5S6B6DSFP-BE |
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Rev 0.3 / July 2004
10
HY5S6B6D(L/S)F(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
COMMAND TRUTH TABLE
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Function
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
0,1
Note
Mode Register Set
Extended Mode Register Set
No Operation
Device Deselect
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst stop
Auto Refresh
Self Refresh Entry
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
L
L
H
X
L
H
H
H
H
L
L
H
L
L
X
H
X
H
X
H
X
V
L
L
H
X
H
L
L
L
L
H
H
H
L
L
X
H
X
H
X
H
X
V
L
L
H
X
H
H
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
OP CODE
OP CODE
X
X
2
2
Row Address
Column
Column
Column
Column
X
X
V
V
V
V
V
X
V
L
H
L
H
H
L
X
X
X
Self Refresh Exit
L
H
X
1
Precharge Power Down Entry
H
L
X
Precharge Power Down Exit
L
H
X
Clock Suspend Entry
H
L
X
Clock Suspend Exit
Deep Power Down Entry
Deep Power Down Exit
L
H
L
H
L
H
X
X
X
X
L
H
H
L
X
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| HY5S6B6DSFP-SE | 4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSF-SE | 4Banks x1M x 16bits Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5S6B6DSFP-SE | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSF-SE | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
| HY5S7B2ALFP-6 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512M (16Mx32bit) Mobile SDRAM |
| HY5S7B2ALFP-6E | 制造商:SK Hynix Inc 功能描述: |
| HY5S7B2ALFP-H | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512M (16Mx32bit) Mobile SDRAM |
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