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參數(shù)資料
| 型號： | HY5PS1G831ALFP-C4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, PBGA68 |
| 封裝： | FBGA-68 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 574K |
| 代理商： | HY5PS1G831ALFP-C4 |
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Rev. 0.7 / Oct. 2007
34
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the
device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calcu-
late these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows
a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by
measuring the signal at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent.
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the
input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to
the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to
the differential data strobe crosspoint for a falling signal applied to the device under test.
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal
and VIL(ac) for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal
and VIH(dc) for a falling signal applied to the device under test.
DQS
VDDQ
VIH(ac)min
VIH(dc)min
tDH
tDS
DQS
VREF(dc)
VSS
VIL(dc)max
VIL(ac)max
tDH
tDS
Differential Input waveform timing
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
VOH + xmV
VOH + 2xmV
VOL + 1xmV
VOL + 2xmV
tHZ
tRPST end point
VTT + 2xmV
VTT + xmV
VTT -xmV
VTT - 2xmV
tHZ
tRPRE begin point
相關PDF資料 |
PDF描述 |
|---|---|
| HY5PS1G831ALFP-Y5 | 128M X 8 DDR DRAM, PBGA68 |
| HY5RS573225AFP-16L | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
| HY5V28CF-S | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| HY5V28CLF-S | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS1G831CFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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