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參數(shù)資料
| 型號： | HY5PS1G831ALFP-C4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, PBGA68 |
| 封裝： | FBGA-68 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 574K |
| 代理商： | HY5PS1G831ALFP-C4 |
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Rev. 0.7 / Oct. 2007
18
HY5PS1G431A(L)FP
HY5PS1G831A(L)FP
HY5PS1G1631A(L)FP
Note :
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed
grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
6.
Definitions for IDD
LOW is defined as Vin
≤ VILAC(max)
HIGH is defined as Vin
≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
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| HY5PS1G831ALFP-Y5 | 128M X 8 DDR DRAM, PBGA68 |
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| HY5V28CF-S | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS1G831CFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831CFP-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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