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參數(shù)資料
| 型號(hào)： | HX6408KBNN |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 25 ns, UUC35 |
| 封裝： | DIE |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 101K |
| 代理商： | HX6408KBNN |
HX6408
8
DYNAMIC ELECTRICAL CHARACTERISTICS
Asynchronous Operation
The RAM in asynchronous in operation, allows the read
cycle to be controlled by address, chip select (NCS), or not
sleep (NSL) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and not sleep (NSL) and write
enable (NWE) must be high. The output drivers can be
controlled independently by the NOE signal. Consecutive
read cycles can be executed with NCS held continuously
low, and with NSL held continuously high, and toggling the
addresses.
For an address activated read cycle, NCS and NSL must
be valid prior to or coincident with the activating address
edge transition(s). Any amount of toggling or skew be-
tween address edge transitions is permissible; however,
data outputs will become valid TAVQV time following the
latest occurring address edge transition. The minimum
address activated read cycle time is TAVAV. When the
RAM is operated at the minimum address activated read
cycle time, the data outputs will remain valid on the RAM
I/O until TAXQX time following the next sequential ad-
dress transition.
To control a read cycle with NCS, all addresses and NSL
must be valid prior to or coincident with the enabling NCS
edge transition. Address or NSL edge transitions can
occur later than the specified setup times to NCS; how-
ever, the valid data access time will be delayed. Any
address edge transition, which occurs during the time
when NCS is low, will initiate a new read access, and data
outputs will not become valid until TAVQV time following
the address edge transition. Data outputs will enter a high
impedance state TSHQZ time following a disabling NCS
edge transition.
To control a read cycle with NSL, all addresses and NCS
must be valid prior to or coincident with the enabling NSL
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to NSL; how-
ever, the valid data access time will be delayed. Any
address edge transition which occurs during the time
when NSL is high will initiate a new read access, and data
outputs will not become valid until TAVQV time following
the address edge transition. Data outputs will enter a high
impedance state TPLQZ time following a disabling NSL
edge transition.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or not sleep (NSL) edge tran-
sitions (refer to Write Cycle timing diagrams). To perform
a write operation, both NWE and NCS must be low, and
NSL must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or
NSL held continuously high. At least one of the control
signals must transition to the opposite state between
consecutive write operations.
The write mode can be controlled via three different
control signals: NWE, NCS, and NSL. All three modes of
control are similar, except the NCS and NSL controlled
modes actually disable the RAM during the write recovery
pulse. NSL fully disables the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity; however, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To write data into the RAM, NWE and NCS must be held
low and NSL must be held high for at least TWLWH/
TSLSH/TPHPH time. Any amount of edge skew between
the signals can be tolerated, and any one of the control
signals can initiate or terminate the write operation. For
consecutive write operations, write pulses must be sepa-
rated by the minimum specified TWHWL/TSHSL/TPLPL
time. Address inputs must be valid at least TAVWL/
TAVSL/TAVPH time before the enabling NWE/NCS/NSL
edge transition, and must remain valid during the entire
write time. A valid data overlap of write pulse width time of
TDVWH/TDVSH/TDVPL, and an address valid to end of
write time of TAVWH/TAVSH/TAVPL also must be pro-
vided for during the write operation. Hold times for address
inputs and data inputs with respect to the disabling NWE/
NCS/NSL edge transition must be a minimum of TWHAX/
TSHAX/TPLPX time and TWHDX/TSHDX/TPLDX time,
respectively. The minimum write cycle time is TAVAV.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HX6408KEFM | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:512k x 8 STATIC RAM |
| HX6408KEFN | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:512k x 8 STATIC RAM |
| HX6408KEHM | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:512k x 8 STATIC RAM |
| HX6408KEHN | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:512k x 8 STATIC RAM |
| HX6408KENM | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:512k x 8 STATIC RAM |
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