參數(shù)資料
型號: HT47C10L(44QFP)
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 16/38頁
文件大小: 287K
代理商: HT47C10L(44QFP)
HT47C10L
Rev. 1.10
16
October 2, 2002
Label (ADCR)
Bits
Function
OVB/OVA
0
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt
which comes from timer A overflow or timer B overflow.
(0= timer A overflow; 1= timer B overflow)
In the timer/event counter mode, this bit is void.
ADC/TM
1
To define 16-bit timer/event counter or RC type A/D converter is enable.
(0= timer/event counter enable; 1= A/D converter is enable)
MODE
2
To define the A/D converter operating mode
0= RREF~CREF oscillation (reference resistor and reference capacitor)
1= RSEN~CREF oscillation (resistor sensor and reference capacitor)
BON
3
Low voltage detector disable/enable (0=disable; 1=enable)
BLF
4
Low voltage flag (0=battery power good; 1=battery low)
5~7
Unused bit, read as 0
ADCR register
Example for RC type AD converter mode (Timer A overflow):
clr tmrc
clr adcr.1
; set timer mode
clr intc.4
; clear timers/event counter interrupt request flag
mov a, low (65536-1000)
; give timer A initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00000010b
; RREF~CREF; set RC type ADC mode; set Timer A overflow
mov adcr, a
mov a, 00h
; give timer B initial value
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 01010000b
; timer A clock source=f
SYS
and timer on
mov tmrc, a
p10:
clr wdt
snz intc.4
; polling timer/event counter interrupt request flag
jmp p10
clr intc.4
; clear timer/event counter interrupt request flag
; program continue
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