參數資料
型號： HT47C10L(44QFP)
英文描述： Microcontroller
中文描述： 微控制器
文件頁數： 15/38頁
文件大?。?/td> 287K
代理商： HT47C10L(44QFP)
HT47C10L
Rev. 1.10
15
October 2, 2002
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RC type A/D converter
RC type A/D converter
RC type A/D converter is implemented in the
HT47C10L. The A/D converter contains two 16-bit pro-
grammable count-up counters and the timer A clock
source comes from the system clock (f
SYS
=32kHz). The
timer B clock source comes from the external RC oscil-
lator. The TMRAL, TMRAH, TMRBL, TMRBH are com-
posed of the A/D converter when ADC/TM bit (bit 1 of
ADCR register) is 1 .
The A/D converter timer B clock source may come from
RREF~RCIN oscillation, RSEN~RCIN oscillation or
RCIN external clock input. The timer A clock source is
the system clock by setting (TN1, TN0=1, 0).
There are six registers related to the A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of ADCR register) decides whether
timer A overflows or timer B overflows, then the TF bit is
set and timer interrupt occurs. When the A/D converter
mode timer A or timer B overflows, the TON bit is reset
and stop counting. Writing TMRAH/TMRBH makes the
starting value be placed in the timer A/timer B and read-
ing TMRAH/TMRBH gets the contents of the timer
A/timer B. Writing TMRAL/TMRBL only writes the data
into a low byte buffer, and writing TMRAH/TMRBH will
write the data and the contents of the low byte buffer into
the timer A/timer B (16-bit) simultaneously. The timer
A/timer B is changed by writing TMRAH/TMRBH opera-
tions and writing TMRAL/TMRBL will keep timer A/timer B
unchanged.
ReadingTMRAH/TMRBHwillalsolatchtheTMRAL/TMRBL
into the low byte buffer to avoid the false timing problem.
Reading TMRAL/TMRBL returns the contents of the low
byte buffer. In other word, the low byte of timer A/timer B
can not be read directly. It must read the TMRAH/TMRBH
first to make the low byte contents of timer A/timer B be
latched into the buffer.
The bit2 of ADCR decides which resistor and capacitor
compose an oscillation circuit and input to TMRBH and
TMRBL.
The TN0 and TN1 bits of TMRC define the clock source
oftimerA.ItissuggestedthattheclocksourceoftimerA
use the system clock.
The TON bit (bit 4 of TMRC) is set 1 the timer A and
timer B will start counting until timer A or timer B over-
flows, the timer/event counter generates the interrupt
requestflag(TF;bit4ofINTC)andthetimerAandtimer
B stop counting and reset the TON bit to 0 at the same
time.
If the TON bit is 1 , the TMRAH, TMRAL, TMRBH and
TMRBL cannot be read or written to. Only when the
timer/event counter is off and when the instruction
MOV is used could those four registers be read or writ-
ten to.
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