參數(shù)資料
型號: HT47C10L(44QFP)
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 10/38頁
文件大?。?/td> 287K
代理商: HT47C10L(44QFP)
HT47C10L
Rev. 1.10
10
October 2, 2002
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC), caused
by a regular time base signal. When the interrupt is en-
abled, and the stack is not full and the TBF bit is set, a
subroutine call to location 08H will occur. The related in-
terrupt request flag (TBF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI instruc-
tion is executed or the EMI bit and the related interrupt
control bit are set to 1 (if the stack is not full). To return
from the interrupt subroutine, RET or RETI instruction
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
Timer/eventcounterinterrupt
1
04H
b
Time base interrupt
2
08H
Oscillator configuration
The HT47C10Lprovidesone built-inRC oscillatorwhich
frequency (f
OSC
) is 32kHz or 128kHz decided by mask
option. However, the CPU system clock (f
SYS
) is always
32kHz. The HALT mode may stop the oscillator decided
bysoftwareoption.Usershouldselect128kHzmaskop-
tion for EL driving mode.
Watchdog timer
WDT
The clock source of the WDT (f
s
) is f
SYS
. The timer is
designedtopreventasoftwaremalfunctionorsequence
jumping to an unknown location with unpredictable re-
sults. The Watchdog timer can be disabled by software
option. If the Watchdog timer is disabled, all the execu-
tions related to the WDT result in no operation.
The HALT instruction is executed, WDT still counts if f
OSC
is on and can wake-up from HALT mode due to the WDT
time-out.
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a warm reset
only the PC and SP are reset to zero. To clear the con-
tents of WDT, three methods are adopted, external reset
(a low level to RES), software instruction, or a HALT in-
struction. The software instruction is CLR WDT. Any ex-
ecution of the CLR WDT instruction will clear the WDT.
The WDT may reset the chip because of the time-out.
TheWDTtime-outperiodrangesfromf
S
/2
15
~f
S
/2
16
.The
CLR WDT instruction only clear the last two-stage of
the WDT.
Multi-function timer
The HT47C10L provides a multi-function timer for the
WDT and time base but with different time-out periods.
The multi-function timer consists of an 8-stage divider
and a 7-bit prescaler, with the clock source coming from
f
SYS
. The multi-function timer also provides a fixed fre-
quency signal (f
S
/8) for the LCD driver circuits, and
buzzer output.
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Control the master or global interrupt (1=enabled; 0=disabled)
1
ETI
Control the timer/event counter interrupt (1=enabled; 0=disabled)
2
ETBI
Control the time base interrupt (1=enabled; 0=disabled)
3
Unused bit, read as 0
4
TF
Timer/event counter interrupt request flag (1=active; 0=inactive)
5
TBF
Time base interrupt request flag (1=active; 0=inactive)
6
Unused bit, read as 0
7
Unused bit, read as 0
INTC Register
7 B
(
*
( ( ( ( ( ( ( (
7 (
( 0 (
A G
< B 3
(
4
.
7
< ; 7
&
(
*
(
. 7
)
(
. 9 ,
.
( )
(
+ ,
.
0 :
.
0 ;
2 2
2 2
1
(
4
B
(
. ( ( ( ,
0 :
.
0 ;
Multi-function timer
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