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參數(shù)資料
| 型號(hào)： | HT23B60-100QFP-A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 60x11 Pixel Data Bank 8-Bit Mask MCU |
| 中文描述： | 60x11像素?cái)?shù)據(jù)銀行8位微控制器面膜 |
| 文件頁數(shù)： | 16/50頁 |
| 文件大?。?/td> | 314K |
| 代理商： | HT23B60-100QFP-A |
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HT23B60
Rev. 1.10
16
March 1, 2004
stack and then branching to subroutines at specified lo-
cations in the program memory. Only the program coun-
ter are pushed and A14~A13 bits onto the stack. If the
contents of the register and Status register (STATUS)
are altered by the interrupt service program which cor-
rupt the desired control sequence, the contents must be
saved first.
External interrupt is triggered by a high to low transition
of INT which sets the related interrupt request flag (EIF;
bit 4 of INTC0). When the interrupt is enabled, and the
stackisnotfullandtheexternalinterruptisactive,asub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer counter 0 interrupt is initialized by set-
ting the timer counter 0 interrupt request flag (T0F; bit 5
of INTC0), caused by a timer counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The timer counter 2 interrupt is operated in the same
manner as Timer counter 0. The related interrupt control
bits ET2I and T2F of timer counter 2 are bit 3 and bit 6 of
INTC0 respectively.
The real time clock interrupt is generated by a 2Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a sub-
routine call to location 14H will occur. The interrupt re-
quest flag RTCF and EMI bits will be cleared to disable
other interrupts.
The keyscan interrupt is generated by LCD enable func-
tion. When the bit7 of the LCDC (2DH) is set 1 , for ev-
ery frame, each have a common signal all of which can
generate a single interrupt. And the keyscan function
have to be completed in the period of interrupt time.
During the execution of an interrupt subroutine, other inter-
rupt acknowledgments are held until the RETI instruction
isexecutedortheEMIbitandtherelatedinterruptcontrolbit
are set to 1 (of course, if the stack is not full). To return from
the interrupt subroutine, the RET or RETI instruction
maybeinvoked.RETIwillsettheEMIbittoenableaninter-
rupt service, but RET will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External interrupt
1
04H
Timer counter 0 overflow
2
08H
Timer counter 2 overflow
3
0CH
Keyscan interrupt
4
10H
RTC interrupt
5
14H
PWM D/A interrupt
6
18H
EMI, EEI, ET0I, ET2I, EKSI, ERTCI, EPWMI are used to
control the enabling/disabling of interrupts. These bits pre-
venttherequestedinterruptfrombeingserviced.Oncethe
interrupt request flags (EIF, T0F, T2F, KSF, RTCF, PWMF)
are set by hardware or software, they will remain in the
INTC0 or INTC1 registers until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well con-
trolled, once a CALL subroutine, if used in the interrupt
subroutine, will corrupt the original control sequence.
Register
Label
Bit No.
Function
INTC0
(0BH)
EMI
0
Master (Global) interrupt (1=enable; 0=disable)
EEI
1
External interrupt (1=enable; 0=disable)
ET0I
2
Timer counter 0 interrupt (1=enable; 0=disable)
ET2I
3
Timer counter 2 interrupt (1=enable; 0=disable)
EIF
4
External interrupt request flag (1=active; 0=inactive)
T0F
5
Internal timer counter 0 request flag. (1=active; 0=inactive)
T2F
6
Internal timer counter 2 request flag. (1=active; 0=inactive)
7
Unused bit, read as 0
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