參數(shù)資料
型號： HT23B60-100QFP-A
廠商： Holtek Semiconductor Inc.
英文描述： 60x11 Pixel Data Bank 8-Bit Mask MCU
中文描述： 60x11像素數(shù)據(jù)銀行8位微控制器面膜
文件頁數(shù)： 10/50頁
文件大?。?/td> 314K
代理商： HT23B60-100QFP-A
HT23B60
Rev. 1.10
10
March 1, 2004
well-defined, the higher-order byte of the table word
are transferred to the TBLH. The Table Higher-order
byte register (TBLH) is read only. The Table Pointer
(TBHP, TBLP) is a read/write register (1FH, 07H),
used to indicate the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR. If this hap-
pens, errors can occur. In other words, using the table
read instruction in the main routine and the ISR simul-
taneously should be avoided. However, if the table
read instruction has to be applied in both the main rou-
tine and the ISR, the interrupts should be disabled
prior to the table read instruction. It should not be en-
abled until the TBLH has been backed up. All table re-
lated instructions need two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon requirements.
Stack Register
STACK
This is a special part of memory which is used to save
the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the con-
tents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction ( RET or RETI ), the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes place,
the interrupt request flag will be recorded but the acknowl-
edge will be inhibited. When the stack pointer is decre-
mented (by RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing the pro-
grammer to use the structure more easily.
In a similar case, if the stack is full and a CALLis subse-
quently executed, stack overflow occurs and the first en-
try will be lost (only the most recent eight return address
are stored).
Data Memory
RAM
The data memory is designed with (192 12) 8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory. Most are read/write, but some are read only.
Bank 0 (BP4~BP0=0000H)
The Bank 0 data memory includes special purpose
and general purpose memory. The special purpose
memory is addressed from 00H to 3FH. The special
function registers include the indirect addressing reg-
isters (IAR0:00H, IAR1:02H), timer counter 0 higher
order byte register (TMR0H: 0CH), timer counter 0
lowerorderbyteregister(TMR0L:0DH),timercounter
0 control register (TMR0C: 0EH), timer 2 lower-order
byte register (TMR2L:2BH), timer 2 higher-order byte
register (TMR2H:2AH), timer 2 control register
(TMR2C:2CH), real timer clock control register (RTC:
24H), program counter lower-order byte register
(PCL: 06H), memory pointer registers (MP0: 01H,
MP1:03H), accumulator (ACC:05H), table pointer
lower-order byte register (TBLP: 07H), table pointer
higher-order byte register (TBHP:1FH), table
higher-order byte register(TBLH:08H), status register
(STATUS:0AH), interrupt control register 0
(INTC0:0BH), interrupt control register 1
(INTC1:1EH), watchdog timer option setting register
(WDTS:09H), PLL control register (OPMODE:26H),
LCD control register (LCDC:2DH), LCD bright control
register (VLCDC:34H), LCD segment output port 0
data register (LCDPC: 37H), LCD segment output
port 0 control register (LCDPCC: 38H), LCD segment
output port 1 data register (LCDPD:39H), LCD seg-
ment output port 1 control register (LCDPDC:3AH),
PFD control register (PFDC:2FH), PWM data register
(PWM:31H), PWM control register (PWMC:30H), se-
rial data register (SRD:33H), serial control register
(SRC:32H), I/O registers (PA:12H, PB:14H) , I/O con-
trol registers (PAC:13H, PBC:15H) and pull-high con-
trol register (PAPHC:35H, PBPHC:36H).
The general purpose data memory, addressed from
40H to FFH, is used for data and control information
under instruction commands. All data memory areas
can handle arithmetic, logic, increment, decrement
and rotate operations directly. Except for some dedi-
cated bits, each bit in the data memory can be set and
reset by the SET [m].i and CLR [m].i instructions,
respectively. They are also indirectly accessible
Instruction
Table Location
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#6
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: @7~@0: TBLP register bit7~bit0
*14~*0: Current program ROM table address bit14~bit0
#6~#0: TBHP register bit6~bit0
相關PDF資料
PDF描述
HT23C010 CMOS 128K x 8-Bit Mask ROM(CMOS 128K x 8位掩模式ROM)
HT23C020 CMOS 256K x 8-Bit Mask ROM(CMOS 256K x 8位掩模式ROM)
HT23C040 CMOS 512K x 8-Bit Mask ROM(CMOS 512K x 8位掩模式ROM)
HT23C128 CMOS 16Kx 8-Bit Mask ROM
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相關代理商/技術參數(shù)
參數(shù)描述
HT23C010 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 128Kⅴ 8-Bit Mask ROM
HT23C020 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 256Kx 8-Bit Mask ROM
HT23C040 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 512Kx8-Bit Mask ROM
HT23C040H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS 512K?8-Bit High Speed Mask ROM
HT23C128 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 16Kx 8-Bit Mask ROM
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