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參數(shù)資料
| 型號(hào)： | HPA00021DGGR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS |
| 中文描述： | 14位注冊(cè)緩沖區(qū)薩里衛(wèi)星技術(shù)有限公司2輸入和輸出 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HPA00021DGGR |
SCES344E
–
DECEMBER 2000
–
REVISED NOVEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
NOM
MAX
UNIT
VCC
VDDQ
VREF
VTT
VI
VIH
VIL
VIH
VIL
VIH
VIL
VICR
VI(PP)
IOH
IOL
TA
NOTE 4: The RESET input of the device must be held at a valid logic level (not floating) to ensure proper device operation. The differential inputs
must not be floating unless RESET is low. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature
number SCBA004.
Supply voltage
VDDQ
2.7
V
Output supply voltage
2.3
2.7
V
Reference voltage (VREF = VDDQ/2)
Termination voltage
1.15
1.25
1.35
V
VREF
–
40mV
VREF
VREF+40mV
VCC
V
Input voltage
0
V
AC high-level input voltage
Data inputs
VREF+310mV
V
AC low-level input voltage
Data inputs
VREF
–
310mV
V
DC high-level input voltage
Data inputs
VREF+150mV
V
DC low-level input voltage
Data inputs
VREF
–
150mV
V
High-level input voltage
RESET
1.7
V
Low-level input voltage
RESET
0.7
V
Common-mode input voltage range
CLK, CLK
0.97
1.53
V
Peak-to-peak input voltage
CLK, CLK
360
mV
High-level output current
–
20
mA
Low-level output current
20
Operating free-air temperature
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC AND
VDDQ
2.3 V
MIN
TYP
MAX
UNIT
VIK
II =
–
18 mA
IOH =
–
100
μ
A
IOH =
–
16 mA
IOL = 100
μ
A
IOL = 16 mA
VI = VCC or GND
RESET = GND
–
1.2
V
VOH
2.3 V to 2.7 V
VDDQ
–
0.2
1.95
V
2.3 V
VOL
2.3 V to 2.7 V
0.2
V
2.3 V
0.35
±
5
10
II
All inputs
2.7 V
μ
A
μ
A
mA
μ
A/
MHz
ICC
Static standby
IO = 0
2 7 V
2.7 V
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
8
56
Dynamic operating
–
clock only
28
ICCD
Dynamic operating
–
per each data input
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at
one-half clock frequency, 50% duty cycle
IO = 0
2.5 V
9
μ
A/
clock
MHz/
D input
rOH
Output high
IOH =
–
20 mA
2.3 V to 2.7 V
7
20
rOL
Output low
IOL = 20 mA
IO = 20 mA, TA = 25
°
C
VI = VREF
±
310 mV
VICR = 1.25 V, VI(PP) = 360 mV
VI = VCC or GND
2.3 V to 2.7 V
7
20
rO(
)
rOH
–
rOL
Data inputs
2.5 V
6
2.5
3
3.5
Ci
CLK, CLK
2.5 V
2.5
3
3.5
pF
RESET
2.5
3
3.5
All typical values are at VCC = 2.5 V, TA = 25
°
C.
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