8 GHz fractional syntHesizer For price" />
參數(shù)資料
型號: HMC703LP4E
廠商: Hittite Microwave Corporation
文件頁數(shù): 9/58頁
文件大小: 0K
描述: IC FRACT-N PLL W/SWEEPR 24QFN
標準包裝: 1
類型: 整數(shù) N/小數(shù) N 分頻
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 8GHz
除法器/乘法器: 是/無
電源電壓: 3.3V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標準包裝
其它名稱: 1127-1065-6
P
LL
s
-
s
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T
6 - 17
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
Figure 28.
-180
-160
-140
-120
-100
-80
-60
-40
-20
100
1000
10
4
10
5
10
6
10
7
10
8
PH
ASE
N
O
ISE
(d
Bc
/H
z
)
FREQUENCY OFFSET (Hz)
PLL at 1 kHz
VCO at 1 kHz
PLL Floor
VCO at 1 MHz
Figure of Merit Example
It should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame-
ters and one should use a more complete design tool such as Hittite PLL Design for better estimates of the phase noise
performance. Noise models for each of the components in Hittite PLL Design can be derived from the FOM equations
or can be provided by Hittite applications engineering.
spurious Performance
integer operation
The VCO always operates at an integer multiple of the PD frequency in an integer synthesizer. In general, spurious
signals originating from an integer synthesizer can only occur at multiples of the PD frequency. These unwanted outputs
are often simply referred to as reference sidebands.
spurs unrelated to the reference frequency must originate from outside sources. External spurious sources can
modulate the VCO indirectly through power supplies, ground, or output ports, or bypass the loop filter due to poor
isolation of the filter. It can also simply add to the output of the synthesizer.
The HMC703LP4E has been designed and tested for ultra-low spurious performance. Reference spurious levels are
typically below -100 dBc with a well designed board layout. A regulator with low noise and high power supply rejection,
such as the HMC860LP3E, is recommended to minimize external spurious sources.
Reference spurious levels of below -100 dBc require superb board isolation of power supplies, isolation of the VCO
from the digital switching of the synthesizer and isolation of the VCO load from the synthesizer. Typical board layout,
regulator design, demo boards and application information are available for very low spurious operation. Operation
with lower levels of isolation in the application circuit board, from those recommended by Hittite, can result in higher
spurious levels.
Of course, if the application environment contains other interfering frequencies unrelated to the PD frequency, and if
the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies
will mix with the desired synthesizer output and cause additional spurs. The level of these spurs is dependant upon
isolation and supply regulation or rejection (PsRR).
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