8 GHz fractional syntHesizer For price" />
參數(shù)資料
型號(hào)： HMC703LP4E
廠商： Hittite Microwave Corporation
文件頁(yè)數(shù)： 27/58頁(yè)
文件大小： 0K
描述： IC FRACT-N PLL W/SWEEPR 24QFN
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 整數(shù) N/小數(shù) N 分頻
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 8GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤(pán)（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： 1127-1065-6
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
With this simplification the total integrated VCO phase noise, Ф2v, in rads2 is given by
Ф2v= Ф2(f0) Вπ
where
Ф2 is the single sideband phase noise in rads2/Hz inside the loop bandwidth, and
В is the 3 dB corner frequency of the closed loop PLL
The integrated phase noise at the phase detector, Ф2pd, is just scaled by N2 ie. Ф2pd = Ф2v/N2
The rms phase jitter of the VCO (Фv) in rads, is just the square root of the phase noise integral.
since the simple integral of (EQ 10) is just a product of constants, we can easily do the integral in the log domain. For
example if the phase noise inside the loop is -110 dBc/Hz at 10 kHz offset and the loop bandwidth is 100 kHz, and the
division ratio is 100, then the integrated phase noise at the phase detector, in dB, is given by;
Ф2pd = 10log(Ф2(f0) Вπ/N2) = -110 + 5 + 50 - 40 = -95 dBrads, or equivalently
95
20
10
=
= 18 rads = 1 milli-degrees
rms.
While the phase noise reduces by a factor of 20logN after division to the reference, due to the increased period of the
PD reference signal, the jitter is constant.
The rms jitter from the phase noise is then given by Tjpn=Tpd Ф2pd/2π
In this example if the PD reference was 50 MHz, Tpd = 20 nsec, and hence Tjpn = 56 femto-sec.
charge Pump and Phase Detector
The Phase Detector or PD has two inputs, one from the reference path divider and one from the RF path divider. When
in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with
respect to each other. We refer to the frequency of operation of the PD as fpd. Most formula related to step size, delta-
sigma modulation, timers etc., are functions of the operating frequency of the PD, fpd is sometimes referred to as the
comparison frequency of the PD.
The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump
output current as a linear function of the phase difference between the two signals. The output current varies in a linear
fashion over nearly ±2π radians (±360) of input phase difference.
charge Pump and Phase Detector functions
Phase detector register Reg 0Bh allows manual access to control special phase detector features.
Reg 0Bh[2:0] allows fine tuning of the PD reset path delay. This adjustment can be used to improve performance at very
high PD rates. Most often this register is set to the recommended value only.
Reg 0Bh[5] and [6] enables the PD UP and DN outputs respectively. Disabling prevents the charge pump from pumping
up or down respectively and effectively tri-states the charge pump while leaving all other functions operating internally.
CP Force UP Reg 0Bh[7] and CP Force DN Reg 0Bh[8] allows the charge pump to be forced up or down respectively.
This will force the VCO to the ends of the tuning range which can be useful for testing of the VCO.
(eQ 10)
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