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參數(shù)資料
| 型號： | HI7191IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP20 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 187K |
| 代理商： | HI7191IP |
1902
Pin Descriptions
20 LEAD
DIP, SOIC
PIN NAME
DESCRIPTION
1
SCLK
Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the
falling edge.
2
SDO
Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
3
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
4
CS
Chip Select Input. Used to select the HI7191 for a serial data transfer cycle. This line can be tied to DGND.
5
DRDY
An Active Low Interrupt indicating that a new data word is available for reading.
6
DGND
Digital Supply Ground.
7
AV
SS
V
RLO
V
RHI
V
CM
V
INLO
V
INHI
Negative Analog Power Supply (-5V).
8
External Reference Input. Should be negative referenced to V
RHI
.
External Reference Input. Should be positive referenced to V
RLO
.
Common Mode Input. Should be set to halfway between AV
DD
and AV
SS
.
Analog Input LO. Negative input of the PGIA.
9
10
11
12
Analog Input HI. Positive input of the PGIA. The V
INHI
input is connected to a current source that can be used to check
the condition of an external transducer. This current source is controlled via the Control Register.
13
AV
DD
AGND
Positive Analog Power Supply (+5V).
14
Analog Supply Ground.
15
DV
DD
OSC
2
OSC
1
Positive Digital Supply (+5V).
16
Used to connect a crystal source between OSC
1
and OSC
2
. Leave open otherwise.
Oscillator Clock Input for the device. A crystal connected between OSC
1
and OSC
2
will provide a clock to the
device, or an external oscillator can drive OSC
1
. The oscillator frequency should be 10MHz (Typ).
Active Low Reset Pin. Used to initialize the HI7191 registers, filter and state machines.
17
18
RESET
19
SYNC
Active Low Sync Input. Used to control the synchronization of a number of HI7191s. A logic ‘0’ initializes the converter.
20
MODE
Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking
(Mode = 0) for the Serial Port.
Load Test Circuit
FIGURE 4.
V
1
R
1
C
L
(INCLUDES STRAY
CAPACITANCE)
DUT
ESD Test Circuits
FIGURE 5A.
FIGURE 5B.
DUT
HUMAN BODY
C
ESD
= 100pF
R
1
= 10M
R
2
= 1.5k
MACHINE MODEL
C
ESD
= 200pF
R
1
= 10M
R
2
= 0
R
1
C
ESD
R
2
±
V
CHARGED DEVICE MODEL
R
1
= 1G
R
2
= 1
R
1
R
2
±
V
DUT
DIELECTRIC
HI7191
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