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參數(shù)資料
| 型號： | HI7191IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP20 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 187K |
| 代理商： | HI7191IP |
1911
It is important to realize that the user can interrupt a data
transfer on byte boundaries. That is, if the Instruction Regis-
ter calls for a 3 byte transfer and CS is inactive after only one
byte has been transferred, the HI7191, when reactivated, will
continue with the remaining two bytes before looking for the
next Instruction Register write cycle.
Note that the outputs will NOT go three-state immediately upon
CS inactive for read operations in self-clocking mode. In the
case of CS going inactive during a read cycle the outputs
remain driving until after the last data bit is transferred. In the
case of CS inactive during the clock stall time it takes 1 OSC
1
cycle plus prop delay (Max) for the outputs to be disabled.
I/O Port Pin Descriptions
The serial I/O port is a bidirectional port which is used to
read the data register and read or write the control register
and calibration registers. The port contains two data lines, a
synchronous clock, and a status flag. Figure 12 shows a
diagram of the serial interface lines.
SDO
- Serial Data out. Data is read from this line using those
protocols with separate lines for transmitting and receiving
data. An example of such a standard is the Motorola Serial
Peripheral Interface (SPI) using the 68HC05 and 68HC11
family of microcontrollers, or other similar processors. In the
case of using bidirectional data transfer on SDIO, SDO does
not output data and is set in a high impedance state.
SDIO
- Serial Data in or out. Data is always written to the
device on this line. However, this line can be used as a bidi-
rectional data line. This is done by properly setting up the
Control Register. Bidirectional data transfer on this line can
be used with Intel standard serial interfaces (SSR, Mode 0)
in MCS51 and MCS96 family of microcontrollers, or other
similar processors.
SCLK
- Serial clock. The serial clock pin is used to synchro-
nize data to and from the HI7191 and to run the port state
machines. In Synchronous External Clock Mode, SCLK is
configured as an input, is supplied by the user, and can run
up to a 5MHz rate. In Synchronous Self Clocking Mode,
SCLK is configured as an output and runs at OSC
1
/8.
CS
- Chip select. This signal is an active low input that
allows more than one device on the same serial communica-
tion lines. The SDO and SDIO will go to a high impedance
state when this signal is high. If driven high during any
communication cycle, that cycle will be suspended until CS
reactivation. Chip select can be tied low in systems that
maintain control of SCLK.
DRDY
- Data Ready. This is an output status flag from the
device to signal that the Data Output Register has been
updated with the new conversion result. DRDY is useful as an
edge or level sensitive interrupt signal to a microprocessor or
microcontroller. DRDY low indicates that new data is available
at the Data Output Register. DRDY will return high upon
completion of a complete Data Output Register read cycle.
MODE
- Mode. This input is used to select between Synchro-
nous Self Clocking Mode (‘1’) or the Synchronous External
Clocking Mode (‘0’). When this pin is tied to V
DD
the serial
port is configured in the Synchronous Self Clocking mode
where the synchronous shift clock (SCLK) for the serial port is
generated by the HI7191 and has a frequency of OSC
1
/8.
When the pin is tied to DGND the serial port is configured for
the Synchronous External Clocking Mode where the synchro-
nous shift clock for the serial port is generated by an external
device up to a maximum frequency of 5MHz.
Programming the Serial Interface
It is useful to think of the HI7191 interface in terms of
communication cycles. Each communication cycle happens
in 2 phases. The first phase of every communication cycle
is the writing of an instruction byte. The second phase is
the data transfer as described by the instruction byte. It is
important to note that phase 2 of the communication cycle
can be a single byte or a multi-byte transfer of data. For
example, the 3-byte Data Output Register can be read
using one multi-byte communication cycle rather than three
single-byte communication cycles. It is up to the user to
maintain synchronism with respect to data transfers. If the
system processor “gets lost” the only way to recover is to
reset the HI7191. Figure 14 shows both a 2-wire and a
3-wire data transfer.
Several formats are available for reading from and writing to
the HI7191 registers in both the 2-wire and 3-wire protocols.
A portion of these formats is controlled by the CR<2:1> (BD
and MSB) bits which control the byte direction and bit order
of a data transfer respectively. These two bits can be written
in any combination but only the two most useful will be dis-
cussed here.
CHIP SELECT
DEVICE STATUS
CLOCK MODE
SDO
SDIO
SCLK
CS
DRDY
MODE
HI7191
BIDIRECTIONAL DATA
PORT CLOCK
DATA OUT
FIGURE 11. HI7191 SERIAL INTERFACE
OSC
1
CS
SCLK
29
33
37
41
45
89
121
125
FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE
HI7191
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