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參數(shù)資料
| 型號(hào)： | HI5634 |
| 廠商： | Intersil Corporation |
| 英文描述： | High Performance Programmable Phase-Locked Loop for LCD Applications |
| 中文描述： | 高性能可編程鎖相環(huán)環(huán)路，用于LCD應(yīng)用 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 131K |
| 代理商： | HI5634 |
7
I
2
C Register Map Summary
REGISTER
NUMBER
NAME
ACCESS
BIT NAME
BIT #
RESET
VALUE
DESCRIPTION
0h
Input Control
R / W
PDEN
0
1
Phase Detector Enable (0 = External Enable, 1 = Always Enabled)
PD_POL
1
0
Phase Detector Enable Polarity (0 = Not Inverted, 1 = Inverted)
REF_POL
2
0
External Reference Polarity (0 = Positive Edge, 1 = Negative Edge)
FBK_POL
3
0
External Feedback Polarity (0 = Positive Edge, 1 = Negative Edge)
FBK_SEL
4
0
External Feedback Select (0 = Internal Feedback, 1 = External)
FUNC_SEL
5
0
Function Out Select (0 = Recovered HSYNC, 1 = Input HSYNC)
EN_PLS
6
1
Enable PLL Lock/Ref Status Output (0 = Disable, 1 = Enable)
EN_DLS
7
0
Enable DPA Lock/Ref Status Output (0 = Disable, 1 = Enable)
1h
Loop Control
R / W
PFD0-2
0-2
0
Phase Detector Gain
Reserved
3
0
Reserved
PSD0-1
4-5
0
Post Scaler Divider (0 =
÷
2, 1 =
÷
4, 2 =
÷
8, 3 =
÷
16)
Reserved
6-7
0
Reserved
2h
FDBK Div 0
R / W
FDB0-7
0-7
FF
PLL Feedback Divider LSBs (Bits 0-7)
3h
FDBK Div 1
R / W
FDB8-11
0-3
F
PLL Feedback Divider MSBs (Bits 8-11)
Reserved
4-7
0
Reserved
4h
DPA Offset
R / W
DPA_OS0-5
0-5
0
Digital Phase Adjustment Offset
Reserved
6
0
Reserved
FIL_SEL
7
0
Loop Filter Select (0 = External, 1 = Internal)
5h
DPA Control
R / W
DPA_RES0-1
0-1
3
DPA Resolution (0 = 16 Delay Elements, 1 = 32, 2 = Reserved, 3 = 64)
METAL_REV
2-7
0
Metal Mask Revision Number
6h
Output Enables
R / W
OE_PCK
0
0
Output Enable for PECL PCLK Outputs (0 = High Z, 1 = Enabled)
OE_TCK
1
0
Output Enable for STTL_3 CLK Output (0 = High Z, 1 = Enabled)
OE_P2
2
0
Output Enable for PECL CLK/2 Outputs (0 = High Z, 1 = Enabled)
OE_T2
3
0
Output Enable for STTL_3 CLK/2 Output (0 = High Z, 1 = Enabled)
OE_F
4
0
Output Enable for STTL_3 FUNC Output (0 = High Z, 1 = Enabled)
CK2_INV
5
0
CLK/2 Invert (0 = Not Inverted, 1 = Inverted)
OUT_SCL
6-7
0
SSTL Clock Scaler (0 =
÷
1, 1 =
÷
2, 2 =
÷
4, 3 =
÷
8)
7h
OSC_DIV
R / W
OSC_DIV 0-6
0-6
0
Osc Divider Modulus
IN_SEL
7
1
Input Select (0 = HSYNC Input, 1 = Osc Divider)
8h
Reset
Write
DPA
0-3
x
Writing xAh Resets DPA and Loads Working Register 5
PLL
4-7
x
Writing 5xh Resets PLL and Loads Working Registers 1-3
10h
Chip Ver
Read
CHIP VER
0-7
17
Chip Version 23 Decimal (17 Hex)
11h
Chip Rev
Read
CHIP REV
0-7
01
Initial Value 01h. Value Increments With Each All Layer Change.
12h
RD_REG
Read
DPA_LOCK
0
N/A
DPA Lock Status (0 = Unlocked, 1 = Locked)
PLL_LOCK
1
N/A
PLL Lock Status (0 = Unlocked, 1 = Locked)
Reserved
2-7
0
Reserved
Identifies Double Buffered Registers. Working Registers are Loaded During Software PLL Reset.
Identifies Double Buffered Registers. Working Registers are Loaded During Software DPA Reset.
HI5634
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HI5634_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
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| HI5640CN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HI-565 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Speed, Monolithic D/A Converter with Reference |
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