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參數(shù)資料
| 型號： | HI5634 |
| 廠商： | Intersil Corporation |
| 英文描述： | High Performance Programmable Phase-Locked Loop for LCD Applications |
| 中文描述： | 高性能可編程鎖相環(huán)環(huán)路，用于LCD應(yīng)用 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 131K |
| 代理商： | HI5634 |
1
File Number
4745
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
I
2
C Bus is a Trademark of Philips Corporation.
PRELIMINARY
HI5634
High Performance Programmable
Phase-Locked Loop for LCD Applications
The HI5634 is a low cost but very high-performance
frequency generator for line-locked and genlocked high
resolution video applications. Utilizing an advanced low
voltage CMOS mixed signal technology, the HI5634 is an
effective clock solution for video projectors and displays at
resolutions from VGA to beyond UXGA
The HI5634 offers pixel clock outputs in both differential (to
250MHz) and single-ended (to 150MHz) formats. Digital
phase adjustment circuitry allows user control of the pixel
clock phase relative to the recovered sync signal. A second
differential output at half the pixel clock rate enables
deMUXing of multiplexed A/D converters. The FUNC pin
provides either the regenerated input from the phase-locked
loop (PLL) divider chain output or a re-synchronized and
sharpened input HSYNC.
The advanced PLL utilizes either its internal programmable
feedback divider or an external divider. The device is
programmed by a standard I
2
C-bus
serial interface.
Simplified Block Diagram
Features
Pixel Clock Frequencies up to 250MHz
Very Low Jitter
Digital Phase Adjustment (DPA) for Clock Outputs
Balanced PECL Differential Outputs
Single-Ended SSTL_3 Clock Outputs
Double-Buffered PLL/DPA Control Registers
Independent Software Reset for PLL/DPA
External or Internal Loop Filter Selection
Uses 3.3V Supply. Inputs are 5V Tolerant.
I
2
C-bus Serial Interface can Run at Either Low Speed
(100kHz) or High Speed (400kHz)
Lock Detection
Applications
LCD Monitors and Video Projectors
Genlocking Multiple Video Subsystems
Frequency Synthesis
Pinout
HI5634
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HI5634CB
0 to 70
24 Ld SOIC
M24.3
PHASE
LOCKED
LOOP
DIGITAL
PHASE
ADJUST
CLK
CLK/2
FUNC
LOOP FILTER
OSC
HSYNC
I
2
C INTERFACE
VDDD
VSSD
SDA
SCL
1
2
3
4
24
23
22
21
IREF
CLK/2+ (PECL)
CLK/2- (PECL)
CLK+ (PECL)
PDEN
EXTFB
HSYNC
EXTFIL
5
6
7
8
20
19
18
17
CLK- (PECL)
VSSQ
VDDQ
CLK (SSTL)
EXTFILRET
VDDA
VSSA
OSC
9
10
11
12
16
15
14
13
CLK/2 (SSTL)
FUNC (SSTL)
LOCK/REF (SSTL)
I
2
CADR
Data Sheet
May 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5634CB | High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5640 | 3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 |
| HI5640CN | Converter IC |
| HI5660EVAL1 | 8-Bit, 165/125/60MSPS, High Speed D/A Converter |
| HI5660IA | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5634_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5634CB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5640 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 |
| HI5640CN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HI-565 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Speed, Monolithic D/A Converter with Reference |
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