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參數(shù)資料
| 型號： | HI3026JCQ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADC FLASH 8BIT 120MSPS 48-PQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 120M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -20°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-BQFP |
| 供應(yīng)商設(shè)備封裝： | 48-MQFP（12x12） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
10
Operating Modes
The HI3026 has two types of operating modes which are selected with Pin 45 (SELECT).
DMUX Mode (See Application Circuits, Figures 18, 19, 20)
Set the SELECT pin to VCC for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is out-
put after being demultiplexed by this 1/2 frequency divided
clock. The 1/2 frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.
When using multiple HI3026 units in parallel in this mode, dif-
ferences in the start timing of the 1/2 frequency divided clock
may cause operation as shown in the figure below. As a coun-
termeasure, the HI3026 is equipped with a function which
resets the 1/2 frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at fC (Min) = 120 MSPS in this mode.
Straight Mode (See Application Circuits, Figures 21, 22, 23)
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
NOTE: Where
σ (LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter tAJ is:
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Test Circuits (Continued)
SIGNAL
SOURCE
COMPARATOR
A > B
PULSE
COUNTER
SIGNAL
SOURCE
HI3026
LATCH
+
1/8
LATCH
A
fC
B
8
16 LSB
2VP-P SINE WAVE
4
-1kHz
VIN
CLK
fC
LOGIC
ALALYZER
HI3026
VIN
CLK
AMP
8
1024
SAMPLES
ECL
BUFFER
OSC1
φ: VARIABLE
OSC2
100MHz
fR
100MHz
VRT
VRM2
VRB
129
128
127
126
125
(LSB)
Δυ
Δt
σ
VIN
CLK
VIN
CLK
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
tAJ = σ /
Δυ
Δt
-------
= σ/ 256
2
----------
x 2
πf
.
TABLE 2. OPERATING MODE TABLE
OPERATING
MODE
SELECT
MAXIMUM
CONVERSION RATE
DATA OUTPUT
CLOCK OUTPUT
DMUX Mode
VCC
120 MSPS
Demultiplexed Output
60 MBPS
The input clock is 1/2 frequency
divided and output at 60MHz.
Straight Mode
GND
100 MSPS
Straight Output 100 MBPS
The input clock is inverted and
output at 100MHz.
HI3026
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