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8.2.2
Register Configuration
Table 8.2 shows the port 1 register configuration.
Table 8.2
Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address
*
Port 1 data direction register
P1DDR
W
H'00
H'FEB0
Port 1 data register
P1DR
R/W
H'00
H'FF60
Port 1 register
Note:
*
Lower 16 bits of the address.
PORT1
R
Undefined
H'FF50
Port 1 Data Direction Register (P1DDR)
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
Bit
Initial value
R/W
:
:
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the TPU is initialized by a
manual reset, the pin states are determined by the P1DDR and P1DR specifications.
Whether the address output pins maintain their output state or go to the high-impedance state in a
transition to software standby mode is selected by the OPE bit in SBYCR.
Modes 1 to 3 and 7*
The corresponding port 1 pins are output ports when P1DDR is set to 1, and input ports when
cleared to 0.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.