- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371797 > HDMP-1638 Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時鐘輸入的千兆位以太網(wǎng)收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | HDMP-1638 |
| 英文描述： | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器芯片，配有雙串行I / O和差分PECL時鐘輸入（帶雙路串行的I / O和差分PECL的時鐘輸入的千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 253K |
| 代理商： | HDMP-1638 |
6
Figure 5: Receiver Section Timing
Figure 6: Receiver Latency
Symbol
Parameter
Units
Min.
Typ.
Max.
f_lock
Frequency Lock at Powerup
μ
s
500
b_sync
[1,2]
Bit Sync Time
bits
2500
t
valid_before
Time Data Valid Before Rising Edge of RBC
nsec
2.5
t
valid_after
Time Data Valid After Rising Edge of RBC
nsec
1.5
t
duty
RBC Duty Cycle
%
40
60
t
A-B[4]
Rising Edge Time Difference Between RBC0 and RBC1
nsec
7.5
8.5
t
_rxlat[3]
Receiver Latency
nsec
22.4
bits
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
=0.1
μ
F.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
4. Guaranteed at room temperature.
HDMP-1638 (Receiver Section)
Timing Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
DATA
DATA
RX[0]-RX[9]
t
valid_before
t
valid_after
RBC1
K28.5
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
BYTSYNC
RBC0
t
A-B
0.8 V
1.4 V
DATA BYTE A
DATA BYTE D
RX[0]-RX[9]
DATA BYTE D
± DINA,B
1.4 V
t_rxlat
R5
R6
R7
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
RBC1/0
DATA BYTE C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-2689 | Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes |
| HDMP1526 | Optoelectronic |
| HDMP2003 | FIBER OPTIC SUPPORT CIRCUIT |
| HDMP2004 | FIBER OPTIC SUPPORT CIRCUIT |
| HDMP2006 | FIBER OPTIC SUPPORT CIRCUIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1646 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1646A | 制造商:Agilent 功能描述:_ |
| HDMP1646AG | 制造商:Agilent Technologies 功能描述: |
| HDMP-1685A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Agilent HDMP-1685A 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface |
| HDMP-1687 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。