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參數(shù)資料
| 型號(hào)： | HDMP-1638 |
| 英文描述： | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器芯片，配有雙串行I / O和差分PECL時(shí)鐘輸入（帶雙路串行的I / O和差分PECL的時(shí)鐘輸入的千兆位以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大?。?/td> | 253K |
| 代理商： | HDMP-1638 |
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14
TRx I/O Definition
NAME
PIN
TYPE
SIGNAL
Byte Sync Output:
An active high output. Used to indicate
detection of either a comma character (0011111XXX). It
is only active when ENBYTSYNC is enabled.
Serial Data Inputs:
High speed inputs. Serial data is
accepted from the
±
DINA inputs when LOOPEN and
RXSEL are both low.
Serial Data Inputs:
High speed inputs. Serial data is
accepted from the
±
DINB inputs when LOOPEN is low
and RXSEL high.
Serial Input Select:
If this pin is held low then
±
DINA
inputs are parallelized. If this pin is held high then
±
DINB inputs are parallelized.
Serial Data Outputs:
High speed outputs. These lines
are active when LOOPEN is set low. When LOOPEN is set
high, these outputs are held static at logic 1. If unused,
remove the 150
pulldown resistors to save power.
Serial Data Outputs:
High speed outputs. These lines
are active when LOOPEN is set low. When LOOPEN is set
high, these outputs are held static at logic 1. If unused,
remove the 150 Ohm pulldown resistors to save power.
Enable Byte Sync Input:
When high, turns on the
internal byte sync function to allow clock synchronization
to a comma character (0011111XXX). When the line is
low, the function is disabled and will not reset registers
and clocks, or strobe the BYTSYNC line.
Logic Ground:
Normally 0 volts. This ground is used for
internal PECL logic. It should be isolated from the noisy
TTL ground as well as possible.
Analog Ground:
Normally 0 volts. Used to provide a
clean ground plane for the receiver PLL and high-speed
analog cells.
Ground:
Normally 0 volts.
TTL Receiver Ground:
Normally 0 volts. Used for the
TTL output cells of the receiver section.
Analog Ground:
Normally 0 volts. Used to provide a clean
ground plane for the PLL and high-speed analog cells.
BYTSYNC
47
O-TTL
-DINA
+DINA
52
53
HS_IN
-DINB
+DINB
55
56
HS_IN
RXSEL
13
I-TTL
-DOUTA
+DOUTA
59
60
HS_OUT
-DOUTB
+DOUTB
62
63
HS_OUT
ENBYTSYNC
24
I-TTL
GND
21
S
25
GND_RXA
51
S
GND_RXHS
57
S
GND_RXTTL
32
33
46
S
GND_TXA
15
S
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