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參數(shù)資料
| 型號： | HDMP-1637A |
| 英文描述： | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| 中文描述： | 千兆以太網(wǎng)序列化/反序列化器（SerDes）與差分PECL時鐘輸入（帶差分PECL的時鐘輸入的千兆位以太網(wǎng)串行器/解串行器） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 249K |
| 代理商： | HDMP-1637A |
5
Figure 4. Transmitter Latency.
Figure 3. Transmitter Section Timing.
HDMP-1637A (Transmitter Section)
Timing Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
t
setup
t
hold
t_txlat
[1]
Parameter
Setup Time
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
1.5
1.0
Typ.
Max.
3.5
4.4
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
DATA
DATA
TX[9]-TX[0]
t
SETUP
t
HOLD
REFCLK
DATA
DATA
DATA
0.0 V AC
2.0 V
0.8 V
DATA BYTE B
DATA BYTE C
TX[0]-TX[9]
DATA BYTE A
± DOUT
0.0 V AC
DATA BYTE B
t_TXLAT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
REFCLK
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| HDMP-1638 | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
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|---|---|
| HDMP-1638 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs |
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