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參數(shù)資料
| 型號： | HDMP-1637A |
| 英文描述： | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| 中文描述： | 千兆以太網(wǎng)序列化/反序列化器（SerDes）與差分PECL時鐘輸入（帶差分PECL的時鐘輸入的千兆位以太網(wǎng)串行器/解串行器） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 249K |
| 代理商： | HDMP-1637A |
14
Startup Procedure
:
The transceiver startup
procedure(s) use the following
conditions: V
CC
= +3.3 V +/- 5%
and REFCLK = 125 MHz +/- 100
ppm.
After the above conditions have
been met, apply valid data using
a balanced code such as 8B/10B.
Frequency lock occurs within
500 ms. After frequency lock,
phase lock occurs within 2500
bit times.
Figure 12. Power Supply Bypass.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be used
and placed as close as possible to
the appropriate power supply
pins of the HDMP-1637A as
shown on the schematic of
Figure 12. All bypass chip
capacitors are 0.1
μ
F. The
V
CC
_RXA and V
CC
_TXA pins are
the analog power supply pins for
the PLL sections. The voltage
into these pins should be clean
with minimum noise. The PLL
loop filter capacitors and their
pin locations are also shown on
Figure 12. Notice that only two
capacitors are required: C
PLLT
for the transmitter and C
PLLR
for
the receiver. Nominal
capacitance is 0.1
μ
F. The
maximum voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small.
The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP-
1637A. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.
RXCAP0
V
CC
_RXTTL
V
CC
_RXTTL
G
TOP VIEW
GND_RXTTL
GND*
V
CC
*
V
CC
*
GND*
GND_TXA
TXCAP1
V
C
_
V
C
_
V
C
G
V
C
G
V
C
*
V
C
*
G
V
C
_
R
*IT IS RECOMMENDED THAT THESE PINS BE CONNECTED TO THE APPROPRIATE
SUPPLY LINE, EITHER V
OR GND, EVEN THOUGH THE PIN IS BONDED TO AN
ISOLATED PAD. REFER TO THE I/O DEFINITIONS SECTION FOR THESE PINS FOR
MORE DETAILS.
** SUPPLY VOLTAGE INTO V
_RXA AND V
_TXA SHOULD BE FROM A LOW NOISE
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 μF.
V
C
G
V
CC
V
CC
**
V
CC
GND_RXTTL
T
V
C
_
G
G
V
C
_
V
C
C
PLLT
V
CC
**
C
PLLR
V
CC
HDMP-1637A
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