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參數(shù)資料
| 型號： | HDMP-1022 |
| 英文描述： | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| 中文描述： | 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O |
| 文件頁數(shù)： | 38/40頁 |
| 文件大?。?/td> | 321K |
| 代理商： | HDMP-1022 |
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653
that the unused differential inputs
be terminated with 50
. The
O-BLL output cell is designed to
deliver TTL swings directly into
50
. The output impedance is
matched to 50
with a VSWR of
less than 2:1 to above 2 GHz. This
output is ideal for driving the
I-H50 input through a 50
cable
and a 0.1 uF coupling capacitor.
The 150
shunt resistor to
ground improves internal DC bias
of the O-BLL differential output
circuit. The O-BLL driver can also
be connected directly into a high
speed 50
oscilloscope. For
optimum performance, both
output should see the same
impedance. It is necessary that all
used O-BLL outputs be terminated
into 50
. Figure 23 shows
various methods of interfacing O-
BLL to I-H50 and standard TTL
logic.
is limited. The typical swing of C2
is
±
0.8 volts, and thus, the
clamping diode should have a
turn-on voltage below 0.8 V, such
as with germanium or schottky
diodes. This will vary with each
application. This diode will also
aid the Tx and Rx in the initial
frequency lock-in process.
Electrical Connections
The electrical I/Os for both the Tx
and Rx are shown in Figures
19-21. The data sheet uses the
prefix, I and O, on the logic type
in order to identify input and
output lines respectively.
Additional information on pin
names and their functions can be
found in the data sheet under
Tx / Rx I/O Definitions
.
I-TTL and O-TTL
These I/O pins are TTL-
compatible. A simplified
schematic diagram of I/O cell is
shown in Figures 21.
High Speed Interface: I-H50 &
O-BLL
The simplified schematic
diagrams of I-H50 and O-BLL is
are shown in Figure 22. The
I-H50 input cell has internal 50
resistors built into the differential
input lines. The termination is
connected via HGND which
isolates the high speed ground
currents from the internal
grounds. The DC level for the
inputs is at 0 V. Since all of the
high speed inputs into G-LINK do
not have a DC component, it is
recommended that I-H50 inputs
be AC coupled with a 0.1
μ
F
capacitor. It is also recommended
Figure 21. I-TTL and O-TTL Simplified Circuit Schematic.
800
72
10 k
V
CC
_TTL
O_TTL
I_TTL
10 k
V
CC
_TTL
V
CC
_Tx
OR
V
CC
_Rx
GND
ESD
PROTECTION
ESD
PROTECTION
GND_TTL
6 k
36
GND_TTL
V
BB
1.4 V
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相關代理商/技術參數(shù) |
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| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
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