- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370499 > HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V PDF資料下載
參數(shù)資料
| 型號(hào)： | HDMP-1022 |
| 英文描述： | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| 中文描述： | 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O |
| 文件頁(yè)數(shù)： | 10/40頁(yè) |
| 文件大小： | 321K |
| 代理商： | HDMP-1022 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)
625
HDMP-1024 (Rx) Timing
Figure 7 is the Rx timing diagram
when the internal PLL is locked to
the incoming serial data. The size
of the input data frame can be
either 20 bits or 24 bits,
depending on the setting of
M20SEL. Independent of the
frame size, STBROUT’s falling
edge is aligned to the data frame’s
boundary, while the rising edge is
in the center of the data frame.
The synchronous outputs,
D0-D19, LINKRDY*, DAV*, CAV*,
FF, ERROR, and FLAG, are
updated for every data frame,
with a delay of t
d1
after the falling
edge of STRBOUT. There is a
latency delay of two frames from
the input of the serial data frame
to the update of the synchronous
outputs.
The state machine outputs,
STAT0, and STAT1, appear with
the falling edge of STRBOUT after
a delay of t
d2
. Referring to Figure
15, if the RESET or ERROR signal
is present, Rx will go into State 0.
After 128 frames, it will go into
State 1. Transitions after that
depend on the training sequence.
Figure 7. HDMP-1024 (Rx) Timing Diagram.
HDMP-1024 (Rx) Timing Characteristics
Tc = 0
°
C to +85
°
C, V
CC
= 4.5 V to 5.5 V
Symbol
t-valid before
Synchronous Output Setup Time at 75 MHz in 16-bit Mode
t-valid after
Synchronous Output Hold Time at 75 MHz in 16-bit Mode
t
d1
Synchronous Output Delay Referenced to the Falling Edge
of STRBOUT. Delay is Measured with Reference to 1.5 V
Logic Threshold
t
d2
State Machine Output Delay Referenced to the Falling
Edge of STRBOUT
Parameter
Units
nsec
nsec
nsec
Min.
3.0
3.0
Typ.
Max.
2.0
nsec
4.0
Note:
Typical Rx STRBOUT duty cycle range is 45% to 65%.
t
d1
D-FIELD
C-FIELD
D00 - D19
LINKRDY*
DAV*, CAV*
FF, ERROR
FLAG
STRBOUT
DIN
CLK
t
d2
STAT1
STAT0
t-VALID BEFORE
t-VALID AFTER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。