參數(shù)資料
型號(hào)： HDD128M72D18RPW
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
中文描述： DDR SDRAM內(nèi)存模塊1024Mbyte（128Mx72bit），在64Mx8，4Banks，8K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存
文件頁(yè)數(shù)： 7/14頁(yè)
文件大小： 459K
代理商： HDD128M72D18RPW
HANBit
HDD128M72D18RPW
URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
AC characteristics
(THESE AC CHARACTERISTICS WERE TESTED ON THE COMPONENT)
DDR333@CL=2.5
DDR266A@CL=2.0
DDR266B@CL=2.5
-16B
-13A
-13B
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
Row cycle time
t
RC
60
65
65
ns
Refresh row cycle time
t
RFC
72
75
75
ns
Row active time
t
RAS
42
70K
45
120K
45
120K
ns
/RAS to /CAS delay
t
RCD
18
20
20
ns
Row precharge time
t
RP
18
20
20
ns
Row active to Row active delay
t
RRD
12
15
15
ns
Write recovery time
t
WR
15
15
15
t
CK
Last data in to Read command
t
WTR
1
1
1
t
CK
Col. address to Col. address delay
t
CCD
1
1
1
t
CK
CL=2.0
7.5
12
7.5
12
10
12
ns
Clock cycle time
CL=2.5
t
CK
6
12
7.5
12
7.5
12
ns
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from CK/CK
t
DQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
t
AC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
t
DQSQ
-
0.45
-
+0.5
-
+0.5
ns
12
Read Preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
0
ns
3
DQS-in hold time
t
WPREH
0.25
0.25
0.25
t
CK
DQS-in falling edge to CK rising-setup time
t
DSS
0.2
0.2
0.2
t
CK
DQS-in falling edge to CK rising hold time
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
0.9
1.1
0.9
1.1
t
CK
Address and Control Input setup time(Fast)
t
IS
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(Fast)
t
IH
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(Slow)
t
IS
0.8
1.0
1.0
ns
i, 6~9
相關(guān)PDF資料
PDF描述
HDD128M72D18RPW-13A DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
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HDD128M72D18RPW-13A 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
HDD128M72D18RPW-13B 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
HDD128M72D18RPW-16B 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
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