參數(shù)資料
型號： HDD128M72D18RPW
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register
中文描述： DDR SDRAM內(nèi)存模塊1024Mbyte（128Mx72bit），在64Mx8，4Banks，8K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存
文件頁數(shù)： 6/14頁
文件大小： 459K
代理商： HDD128M72D18RPW
HANBit
HDD128M72D18RPW
URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
Input / Output Capacitance
(V
DD
= min to max, V
DDQ
= 2.5V
to 2.7V, T
A
= 25
°
C, f = 100MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)
C
IN1
9
11
pF
Input capacitance(CKE0,CKE1)
C
IN2
9
11
pF
Input capacitance(/CS0)
C
IN3
9
11
pF
Input capacitance(CK0~CK2, /CK0~/CK2)
C
IN4
11
12
pF
Input capacitance(DM0~DM7)
C
IN5
14
16
pF
Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
C
OUT1
14
16
pF
Data input/output capacitance (CB0~CB7)
C
OUT2
14
16
pF
DC Characteristics
(V
DD
= 2.7V, T =10
°
C)
Symbol
-16B
(DDR333@CL=2.5)
-13A
(DDR266@CL=2.0)
-13B
(DDR266@CL=2.5)
Unit
Notes
IDD0
2230
2010
2010
mA
IDD1
2500
2280
2280
mA
IDD2P
590
540
540
mA
IDD2F
1420
1290
1290
mA
IDD2Q
950
900
900
mA
IDD3P
1040
990
990
mA
IDD3N
1690
1560
1560
mA
IDD4R
2540
2280
2280
mA
IDD4W
2630
2330
2330
mA
IDD5
3130
2910
2910
mA
Normal
590
540
540
mA
IDD6
Low
Power
560
510
510
mA
Optional
IDD7A
4520
4080
4080
mA
Notes:
Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
PARAMETER
STMBOL
MIN
MAX
UNIT
NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
VREF + 0.35
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
V
IL
(AC)
VREF - 0.31
V
Input Differential Voltage, CK and CK inputs
V
ID
(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
V
IX
(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion.
the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
相關(guān)PDF資料
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