參數(shù)資料
型號(hào)： HC05V7GRS
英文描述： 68HC05V7 General Release Specification
中文描述： 68HC05V7一般版本規(guī)范
文件頁數(shù)： 85/170頁
文件大?。?/td> 980K
代理商： HC05V7GRS
SECTION 11: 16-BIT TIMER
MOTOROLA
Page 71
accompany a successful output compare provided the corresponding interrupt enable bit
(OCIE) is set. After a processor write cycle to the output compare register containing the
MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The
user must write both bytes (locations) if the MSB is written first. A write made only to the
LSB ($17) will not inhibit the compare function. The free-running counter is updated every
four internal bus clock cycles. The minimum time required to update the output compare
register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level register regardless of
whether the output compare flag (OCF) is set or clear.
11.3
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are
used to latch the value of the free-running counter after the corresponding input capture
edge detector senses a defined transition. The level transition that triggers the counter
transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This
delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each
proper signal transition regardless of whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds
to the most recent input capture.
After a read of the input capture register MSB ($14), the counter transfer is inhibited until
the LSB ($15) is also read. This characteristic causes the time used in the input capture
software routine and its interaction with the main program to determine the minimum pulse
period. A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
INPUT CAPTURE REGISTER - $14:$15
NOTE:
The Input Capture pin (TCAP) and the Output Compare pin (TCMP) are
shared with PB7 and PB6 respectively. The timer’s TCAP input is always
connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the
MISCELLANEOUS control register is set. See
7.2.2OCE - Output
compare enable
.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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