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參數(shù)資料
| 型號： | HC05V7GRS |
| 英文描述： | 68HC05V7 General Release Specification |
| 中文描述： | 68HC05V7一般版本規(guī)范 |
| 文件頁數(shù)： | 120/170頁 |
| 文件大小： | 980K |
| 代理商： | HC05V7GRS |
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MOTOROLA
Page 106
SECTION 15: MESSAGE DATA LINK CONTROLLER
MC68HC05V7 Specification Rev. 1.0
If the received message is verified as error-free then the CRC is discarded, the filled Rx
Buffer and the final value of the Rx Buffer pointer are placed into the CPU memory map,
the Received Message Successfully (RXMS) bit in the MDLC Status Register (MSR) is set,
a CPU interrupt request is made (if interrupts are enabled) and the other Rx Buffer and its
pointer are readied for reception of the next message by the MDLC.
The CPU may now randomly read the Rx Buffer. The first data byte received will be located
in the lowest address entry of the Rx Buffer. The rest of the message is located in
contiguous ascending address entries up to the last data byte received, which will be
located in the
n
th entry, where ’n’ is the final value of the Rx Buffer pointer which now
appears in the MDLC Rx Status Register (MRSR).
As long as the CPU has possession of this Rx Buffer, the MDLC will have possession of
the other Rx Buffer and can concurrently receive a second message without conflict with,
or intervention by, the CPU. Once the CPU has finished with the contents of the Rx Buffer,
it may be "given back" to the MDLC by writing
any
value to the MRSR register.
The above sequence is then repeated as long as normal data reception takes place.
If the CPU is unable to return an Rx Buffer
and
the second Rx Buffer becomes filled
and
a
further new message arrives from the J1850 bus then the new message will be ignored by
the MDLC until an Rx Buffer becomes available to receive new data.
If any type of reception error is detected by the MDLC as a message is being received from
the J1850 bus, the internal Rx Buffer pointer will be reset to zero, effectively flushing the
data received so far, and the MDLC will ignore the rest of the message. When this occurs
the MDLC will
not
generate a CPU interrupt request and will silently wait for the next valid
SOF symbol.
This will also happen if a message received from the J1850 bus is longer than 12 bytes
(including CRC byte), and the Receive Block mode (RXBM) bit is
not
set. In both cases,
when the internal Rx Buffer pointer is reset to zero, the associated Rx Buffer array bytes
will not be cleared or changed.
If a message received from the J1850 bus is longer than 12 bytes (including CRC byte),
and the Receive Block mode (RXBM) bit
is
set then reception of the message will be
continued into the next available Rx Buffer. This will repeat until the end of the message is
detected, at which time the residual data bytes will remain in the last Rx Buffer to be filled.
15.3.3
TX BUFFER
The Tx Buffer consists of one 11-byte array, with 8 bits per byte. Only one message may
occupy the Tx Buffer at any time. The Tx Buffer array has an internal register (the ’Tx Buffer
pointer’) associated with it in which the length of the message body is stored.
Following a reset, the CPU has "possession" of the empty Tx Buffer and its associated Tx
Buffer pointer is reset to zero. The Tx Buffer appears in the CPU memory map at this time,
where the CPU may randomly access it. The first data byte of the message to be sent must
be placed in the lowest address entry of the Tx Buffer. The rest of the message must be
placed in contiguous ascending address entries up to the last data byte to be sent, which
is located in the
n
th entry, where ’n’ is the length of the message body to be sent.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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