參數(shù)資料
型號： HB52F168EN
廠商： Hitachi,Ltd.
英文描述： 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
中文描述： 64 MB的無緩沖SDRAM的內存（64 MB的未緩沖同步的DRAM內存）
文件頁數(shù)： 58/71頁
文件大?。?/td> 906K
代理商： HB52F168EN
HB52F88EM-75F, HB52F89EM-75F, HB52F168EN-75F, HB52F169EN-
58
Writing
Refresh
Auto-refresh:
All the banks must be precharged before executing an auto-refresh command. Since the auto-
refresh command updates the internal counter every time it is executed and determines the banks and the
ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cy-
cles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-
Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the
auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh:
After executing a self-refresh command, the self-refresh operation continues while CKE is held
Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-
refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6
μ
s after ex-
iting from self-refresh mode.
Others
Power-down mode:
The SDRAM module enters power-down mode when CKE goes Low in the IDLE state.
In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM module exits from
the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is
not performed.
Clock suspend mode:
By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend mode,
and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence:
The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
CK
Din
in 0
in 1
l = 0 Latency
in 3
DQMB
相關PDF資料
PDF描述
HB52F169EN 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
HB52F89EM 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
HB52R1289E22 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
HB52R1289E22-A6B 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
HB52R1289E22-B6B 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
相關代理商/技術參數(shù)
參數(shù)描述
HB52F168GB-75B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52F168GB-75BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52F168GB-B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM
HB52F328DC-75B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52F328DC-75BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
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