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參數(shù)資料
| 型號： | GS9035CCTJ |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX II -TM GS9035C Serial Digital Reclocker |
| 中文描述： | GENLINX二，商標(biāo)GS9035C串行數(shù)字時鐘恢復(fù)器 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 490K |
| 代理商： | GS9035CCTJ |
GENNUM CORPORATION
20582 - 3
8 of 14
G
4.2 Manual Mode (AUTO/MAN = 0)
In manual mode, the GS9035C divider moduli is fixed. In
this mode, the SS[1:0] pins are inputs and set the divider
moduli according to Table 3.
5. LOCKING
The GS9035C indicates lock when three conditions are
satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to a harmonic.
The GS9035C defines the presence of input data when at
least one data transition occurs every 1μs.
The GS9035C assumes that it is NOT locked to a harmonic
if the pattern
‘
101
’
or
‘
010
’
(in the reclocked data stream)
occurs at least once every t
sys
/3 seconds. Using the
recommended component values, this corresponds to
approximately 150μs. (In a harmonically locked system, all
bit cells are double clocked and the above patterns
become
‘
110011
’
and
‘
001100
’
, respectively.)
5.1 Lock Time
The lock time of the GS9035C depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9035C is changed from one source to another source
which is at a different data rate.
When input data to the GS9035C is removed, the GS9035C
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9035C begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9035C locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:
In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described in section 2,
Frequency Acquisition
. In
manual mode, the frequency acquisition circuit may have to
sweep over an entire cycle (depending on initial conditions)
to acquire lock resulting in a maximum lock time of 2T
cycle
+
2t
sys
. In auto tune mode, the maximum lock time is 6T
cycle
+
2t
sys
since the frequency acquisition circuit may have to
cycle through 5 possible counter states (depending on
initial conditions) to acquire lock. The nominal value of T
cycle
for the GS9035C operating in a typical SMPTE 259M
application is approximately 1.3ms.
The GS9035C has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5μs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
TABLE 2: Data Rate Indication in Auto Mode
AUTO/MAN = 1 (Auto Mode)
H
,
L
= VCO center frequency as per Figure 10
SMPTE
SS[1:0]
DIVIDER
MODULI
PLL CLOCK
1
00
4
H
/4
1
01
2
L
/2
1
10
2
H
/2
1
11
1
L
0
00
4
H
/4
0
01
4
H
/4
0
10
2
H
/2
0
11
2
H
/2
TABLE 3: Data Rate Select in Manual Mode
AUTO/MAN = 0 (Manual Mode)
H
,
L
= VCO center frequency as per Figure 10
SMPTE
SS[1:0]
DIVIDER
MODULI
PLL CLOCK
1
00
4
H
/4
1
01
2
L
/2
1
10
2
H
/2
1
11
1
L
0
00
4
H
/4
0
01
4
H
/4
0
10
2
H
/2
0
11
2
H
/2
TABLE 4: Lock Time Relative to Switching Time
SWITCHING TIME
LOCK TIME
<0.5μs
10μs
0.5μs - 10ms
2t
sys
>10ms
2T
cycle
+ 2t
sys
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