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參數(shù)資料
| 型號： | GS9035CCTJ |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX II -TM GS9035C Serial Digital Reclocker |
| 中文描述： | GENLINX二，商標(biāo)GS9035C串行數(shù)字時(shí)鐘恢復(fù)器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 490K |
| 代理商： | GS9035CCTJ |
GENNUM CORPORATION
20582 - 3
6 of 14
G
DETAILED DESCRIPTION
The GS9035C receives either a single-ended or differential
PECL serial data stream at the DDI and DDI inputs. It locks
an internal clock to the incoming data and outputs the
differential PECL retimed data signal and recovered clock
on outputs SDO/SDO and SCO/SCO respectively. The
timing between the input, output, and clock signals is
shown below.
Fig. 8 Input/Output Clock Signal Timing
The GS9035C reclocker contains four main functional
blocks: the Phase Locked Loop, Auto/Manual Data Rate
Select, Frequency Acquisition, and Logic Circuit.
1. PHASE LOCKED LOOP (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
Fig. 9 Simplified Diagram of the PLL
1.1 VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 143 and 360Mb/s and has a pull range of
-13 +25% about the center frequency depending on the
signal data rate. A single low impedance external resistor,
R
VCO
, sets the VCO center frequency
(see Figure 9).
The
low impedance R
VCO
minimizes thermal noise and reduces
the PLL's sensitivity to PCB noise.
For a given R
VCO
value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the
L
curve. For all other
SMPTE/SS0 combinations, the VCO center frequency
corresponds to the
H
curve (
H
is approximately 1.5 x
L
).
Fig. 10 VCO Frequency vs. R
VCO
The recommended R
VCO
value for auto rate SMPTE 259M
applications is 365
.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 360Mb/s. The divider modulus is set
by
the
AUTO/MAN,
SMPTE,
(see Auto/Manual Data Rate Select section for further
details).
and
SS[1:0]
pin
When the input data stream is removed for an excessive
period of time
(see AC electrical characteristics table),
the
VCO frequency can drift from the previously locked
frequency up to the maximum shown in Table 1.
DDI
SDO
SCO
50%
DDI/DDI
LF+
LFS
LF-
R
VCO
VCO
DIVISION
R
LF
C
LF1
C
LF2
2
PHASE
DETECTOR
INTERNAL
PLL CLOCK
CHARGE
PUMP
LOOP
FILTER
TABLE 1: Frequency Drift Range (when PLL loses lock)
LOSES LOCK FROM
MIN (%)
MAX(%)
143Mb/s lock
-21
21
177Mb/s lock
-12
26
270Mb/s lock
-13
28
360 Mb/s lock
-13
24
0
100
200
300
400
500
600
700
800
0
200
400
600
800
1000
1200
1400
1600
1800
V
R
VCO
()
H
L
SMPTE=1
SSO=1
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