- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299163 > GS882Z36BGD-225T (GSI TECHNOLOGY) 256K X 36 ZBT SRAM, 6 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | GS882Z36BGD-225T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 36 ZBT SRAM, 6 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 1057K |
| 代理商： | GS882Z36BGD-225T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
Rev: 1.00b 12/2002
25/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36BB/D-250/225/200/166/150/133
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GSCB01C-6Q01 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.55A, 125VDC, 17.3mm, PANEL MOUNT-THREADED |
| GSCB03C-6 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.55A, 125VDC, 17.3mm, PANEL MOUNT-THREADED |
| GSCB33C-6 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, 17.3mm, PANEL MOUNT-THREADED |
| GSCB36C-C021 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, 17.3mm, PANEL MOUNT-THREADED |
| GSCB04C-Q04 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.55A, 125VDC, 17.3mm, PANEL MOUNT-THREADED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS882Z36CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-250V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-300 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 119FPBGA - Trays |
| GS882Z36CD-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
| GS882Z36CD-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。