參數(shù)資料
型號: GS8180S18
廠商: GSI TECHNOLOGY
英文描述: 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述: 1兆x 18位獨立的I / O西格瑪?shù)腄DR SRAM的(100萬× 18位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
文件頁數(shù): 20/32頁
文件大小: 853K
代理商: GS8180S18
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-275
-250
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Clock Cycle Time
tKHKH
3.0
3.3
3.6
4.0
ns
Clock High to Output Valid
tKHQV
1.6
1.8
1.9
2.1
ns
Clock High to Output in High-Z
tKHQZ
0.5
1.6
0.5
1.8
0.5
1.9
0.5
2.1
ns
1
Clock High to Output Invalid
tKHQX
0.5
0.5
0.5
0.5
ns
Clock High to Output in Low-Z
tKHQX1
0.5
0.5
0.5
0.5
ns
1
Clock High to Echo Clock Low-Z
tKHCX1
0.5
0.5
0.5
0.5
ns
2, 4
Clock High to Echo Clock High
tKHCH
0.6
1.5
0.6
1.7
0.6
1.8
0.6
2.0
ns
4
Clock Low to Echo Clock Low
tKLCL
0.6
1.7
0.6
1.8
0.6
2.0
0.6
2.2
ns
4
Output Invalid to Echo Clock High
tCHQX
–0.5
–0.6
–0.6
–0.7
ns
2
Echo Clock High to Output Valid
tCHQV
0.5
0.6
0.6
0.7
ns
2
Clock High to Echo Clock High-Z
tKHCZ
0.5
1.5
0.5
1.7
0.5
1.8
0.5
2.0
ns
1, 2
Clock HIGH Time
tKHKL
1.2
1.3
1.4
1.6
ns
Clock LOW Time
tKLKH
1.2
1.3
1.4
1.6
ns
Address Valid to Clock High
tAVKH
0.6
0.7
0.7
0.8
ns
Clock High to Address Don’t Care
tKHAX
0.4
0.4
0.5
0.5
ns
Enable Valid to Clock High
tEVKH
0.6
0.7
0.7
0.8
ns
Clock High to Enable Don’t Care
tKHEX
0.4
0.4
0.5
0.5
ns
Write Valid to Clock High
tWVKH
0.6
0.7
0.7
0.8
ns
Clock High to Write Don’t Care
tKHWX
0.4
0.4
0.5
0.5
ns
Data In Valid to Clock High
tDVKH
0.6
0.7
0.7
0.8
ns
Clock High to Data In Don’t Care
Notes:
1.
Measured at 100 mV from steady state. Not 100% tested.
2.
Guaranteed by design. Not 100% tested.
3.
For any specific temperature and voltage tKHCZ < tKHCX1.
4.
Tested using AC Test Load B
tKHDX
0.4
0.4
0.5
0.5
ns
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