參數(shù)資料
型號: GS8180S18
廠商: GSI TECHNOLOGY
英文描述: 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述: 1兆x 18位獨立的I / O西格瑪?shù)腄DR SRAM的(100萬× 18位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
文件頁數(shù): 19/32頁
文件大小: 853K
代理商: GS8180S18
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
19/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
Operating Currents
Parameter
Test Conditions
Symbol
-333
-300
-275
-250
Units
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
Operating
Current
E1
V
IL
Max.
tKHKH
tKHKH Min.
All other inputs
V
IL
V
IN
V
IH
I
DDP
Pipeline
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
Bank Deselect
Current
E2 or E3 False
tKHKH
tKHKH Min.
All other inputs
V
IL
V
IN
V
IH
I
SB1
Pipeline
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
Chip Disable
Current
E1
V
IH
Min.
tKHKH
tKHKH Min.
All other inputs
V
IL
V
IN
V
IH
I
SB2
Pipeline
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
CMOS Deselect
Current
Device Deselected
All inputs
V
SS
+ 0.10 V
V
IN
V
DD
– 0.10 V
I
DD3
Pipeline
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
Note: Power measured with outputs disconnected.
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GS8180S09 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
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