參數(shù)資料
型號: GS8170DD36C-300I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
中文描述: 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 6/29頁
文件大?。?/td> 537K
代理商: GS8170DD36C-300I
GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
6/29
2002, GSI Technology, Inc.
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.
The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter
generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM
by driving the ADV pin low, into Load mode.
SigmaRAM DDR Burst Read with Counter Wrap-around
Counter Wraps
QA2
QA3
QA0
QA1
QA2
QA3
QB0
QB1
ADV
B3
A2
B0
CQ
DQ
/E
1
/W
XX
Internal
Address
A2
A0
B2
B1
A3
Continue
A1
A3
B1
B0
CK
XX
Read
Continue
External
Address
A2
XX
XX
Continue
Read
相關(guān)PDF資料
PDF描述
GS8170DD36C-333 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DD36C-333I 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DW36AC 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-333I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-350 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8170DW36AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
GS8170DW36AC-350 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
GS8170DW36AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
GS8170DW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8170DW36AGC-250I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays