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參數(shù)資料
| 型號(hào)： | GS8170DD36C-300I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大小： | 537K |
| 代理商： | GS8170DD36C-300I |
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GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
23/29
2002, GSI Technology, Inc.
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the
RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8170DD36C-333 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-333I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DW36AC | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36AGC-333I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW36AGC-350 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8170DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
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