- 您現在的位置：買賣IC網 > PDF目錄383036 > GS8170DD36C-250 (GSI TECHNOLOGY) 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM PDF資料下載
參數資料
| 型號： | GS8170DD36C-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數： | 4/29頁 |
| 文件大?。?/td> | 537K |
| 代理商： | GS8170DD36C-250 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
4/29
2002, GSI Technology, Inc.
Read Operations
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, the Double Data Rate protocol doubles the
data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In
Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The
output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to
the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Double Data Rate Write
A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both
rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address
and command.
Double Data Rate Pipelined Read
QA0
QA1
QC0
QC1
QD0
QD1
CK
Read
Deselect
A
XX
F
Read
Read
Read
ADV
D
E
C
/E
1
/W
DQ
Address
CQ
Key
Hi-Z
Access
相關PDF資料 |
PDF描述 |
|---|---|
| GS8170DD36C-250I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-300 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-300I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-333 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-333I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8170DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。