參數(shù)資料
型號: GS8170DD36C-250
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
中文描述: 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 20/29頁
文件大?。?/td> 537K
代理商: GS8170DD36C-250
GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
20/29
2002, GSI Technology, Inc.
Timing Parameter Key—DDR Control and Data In Timing
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
tKHnX
tnVKH
tAVKH
tKHAX
CK
A
A
B
C
E1, E2, E3,
W, ADV
tKHDX
tDVKH
DA1
DA2
tKLDX
tDVKL
DDR Write
DQ (Data In)
Note: tnVKH = tEVKH, tWVKH, etc. and tKHnX = tKHEX, tKHWX, etc.
DB1
DB2
相關(guān)PDF資料
PDF描述
GS8170DD36C-250I 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DD36C-300 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DD36C-300I 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DD36C-333 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
GS8170DD36C-333I 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM
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