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參數資料
| 型號： | GM71S4400CJ-70 |
| 廠商： | LG Corp. |
| 英文描述： | 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM |
| 中文描述： | 1,048,576字× 4位的CMOS動態(tài)隨機存儲器 |
| 文件頁數： | 8/9頁 |
| 文件大?。?/td> | 104K |
| 代理商： | GM71S4400CJ-70 |
LG Semicon
GM71C(S)4400C/CL
8
t
WCS
, t
RWD
, t
CWD
t
CPW
and t
AWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
WCS
>=t
WCS
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
RWD
>=t
RWD
(min), t
CWD
>=t
CWD
(min), t
AWD
>=t
AWD
(min) and t
CPW
>=t
CPW
(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or a read modify write cycle.
t
RASP
defines RAS pulse width in fast page mode cycles.
Access time is determined by the longer of t
AA
or t
CAC
or t
ACP
.
An initial pause of 100us is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
Test mode operation specified in this data sheet is 2-bit test function controlled by control
address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is low level. In order to end this test mode operation, perform a RAS
only refresh cycle or a CAS-before-RAS refresh cycle.
In a test mode read cycle, the value of t
RAC
, t
AA
, t
CAC,
t
OAC
and t
ACP
is delayed for 2ns to 5ns for
the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
10.
11.
12.
13.
14.
15.
16.
17.
相關PDF資料 |
PDF描述 |
|---|---|
| GM71C4400CLJ-60 | 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM |
| GM71C4400CLJ-70 | 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM |
| GMA01 | Very High-Speed Switching, Bias Stabilizing Applications |
| GMA01U | Very High-Speed Switching, Bias Stabilizing Applications |
| GMA02 | Very High-Speed Switching Diode |
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| GM71VS16163CLT-60 | 制造商:Logical Devices 功能描述: |
| GM71VS18163CLT-6 | 制造商:HYUNDAI 功能描述:1M X 16 EDO DRAM, 60 ns, PDSO44 |
| GM71VS18163CLT-60 | 制造商:Hyundai 功能描述: |
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