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參數(shù)資料
| 型號(hào)： | FIN12ACGFX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary) |
| 中文描述： | LINE TRANSCEIVER, PBGA42 |
| 封裝： | 3.50 MM, LEAD FREE, MO-195, BGA-42 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 1819K |
| 代理商： | FIN12ACGFX |
Preliminary
13
www.fairchildsemi.com
F
Serializer AC Electrical Characteristics
Serializer Timing Characteristics
Note 7:
Skew is measured from either the rising or falling edge of the bit clock (CKSO) relative to the rising or falling edge of the data bit (DSO). CKSO and
DSO have been designed to be edge aligned.
PLL Specifications
Note 8:
This jitter specification is based on the assumption that PLL has a Ref Clock with cycle-to-cycle input jitter less than 2ns.
Note 9:
The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The
specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Deserializer AC Electrical Characteristics
Note 10:
Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high
state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output
skew from the serializer, load variations and ISI and jitter effects.
Note 11:
Rising edge of CKP will appear approximately 7-bit times after the falling edge of the CKP output. Data will appear coincident with this falling edge.
Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to STROBE for the serializer the
CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain in 7 bit times.
Symbol
t
TLH
t
THL
t
STC
t
HTC
t
TCCD
Parameter
Test Conditions
Min
Typ
0.6
0.6
Max
0.9
0.9
Units
ns
ns
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
See Figure 19
DP[n] Setup to STROBE
DP[n] Hold to STROBE
Transmitter Clock Input to
DIRI
1
See Figure (f
10 MHz)
See Figure , DIRI
1,
2.5
0
ns
ns
TBD
TBD
TBD
ns
Clock Output Delay
CKSO Position Relative to DS
CKREF
STROBE
See Figure , (Note )
CKREF Serialization Mode
t
SK(P-P)
TBD
TBD
TBD
ps
See Figure , (Note )
No CKREF Serialization Mode
TBD
TBD
TBD
Symbol
t
JCC
t
TPLLS0
t
TPLLD0
t
TPLLD1
Test Conditions
Min
Typ
TBD
Max
Units
ns
Cycles
CKSO Clock Out Jitter (Cycle-to-Cycle)
Serializer Phase Lock Loop Stabilization Time See Figure
(Note )
1000
PLL Disable Time Loss of Clock
PLL Power-Down Time
See Figure , (Note )
See Figure
3.0
10.0
20.0
us
ns
Symbol
t
S_DS
t
H_DS
t
RCOP
t
RCOL
t
RCOH
Parameter
Test Conditions
Min
500
Typ
Max
Units
ps
Serial Port Setup Time DS to CKSI
See Figure , (Note )
Serial Port Hold Time DS to CKSI
Deserializer Clock Output (CKP OUT) Period See Figure 23
CKP OUT Low Time
See Figure , (Note )
500
17.8
7a 3
ps
ns
ns
T
200
7a 3
See Figure 23 (Rising Edge Strobe)
Serializer Source STROBE
CKREF
Where a
(1/f)/14 (Note )
See Figure 23 (Rising Edge Strobe)
Where a
(1/f)/14 (Note )
C
L
8pF
See Figure
CKP OUT High Time
7a 3
7a 3
ns
t
PDV
Data Valid to CKP HIGH
7a 3
7a
7a 3
ns
t
ROLH
t
ROHL
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
3.5
3.5
7.0
7.0
ns
ns
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