參數(shù)資料
型號(hào)： F49L004BA
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 4 Mbit (512K x 8) 3V Only CMOS Flash Memory
中文描述： 4兆位（為512k × 8）3V時(shí)僅閃存的CMOS
文件頁(yè)數(shù)： 9/46頁(yè)
文件大?。?/td> 371K
代理商： F49L004BA
EFS T
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 9/46
Output Disable Mode
With the
OE
is at a logic high level (V
IH
), outputs from
the devices are disabled. This will cause the output pins
in a high impedance state
Standby Mode
When
CE
and
the device enter CMOS Standby mode. If
CE
and
are held at V
IH
, but not within the range of V
CC
± 0.3V, the device will still be in the standby mode, but
the standby current will be larger.
ESET
R
are both held at V
CC
± 0.3V,
ESET
R
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
current I
CC2
until the operation is completed. I
CC3
in the
DC Characteristics table represents the standby current
specification.
The device requires standard access time (t
CE
) for read
access from either of these standby modes, before it is
ready to read data.
Sector Protect / Un-protect Mode
The hardware sector protect feature disables both
program and erase operations in any sector. The
hardware sector unprotect feature re-enables both the
program and erase operations in previously protected
sectors. Sector protect/unprotect can be implemented
via two methods.
The primary method requires V
ID
on the
only, and can be implemented either in-system or via
programming equipment.
ESET
R
pin
Figure 16 shows the algorithms and Figure 15 shows
the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect,
all unprotected sectors must first be protected prior to
the first sector unprotect write cycle.
The alternate method intended only for programming
equipment requires V
ID
on address pin A9,
OE
, and
ESET
R
.
Auto-select Mode
The auto-select mode provides manufacturer and
device identification and sector protection verification,
through outputs on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its
corresponding programming algorithm. However, the
auto-select codes can also be accessed in-system
through the command register.
When using programming equipment, this mode
requires V
ID
(11.5 V to 12.5 V) on address pin A9. While
address pins A3, A2, A1, and A0 must be as shown in
Table 4.
To verify sector protection, all necessary pins have to
be set as required in Table 4, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in Table 5. This method
does not require V
ID
. See “ Software Command
Definitions” for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or
sequences into the command register initiates the
device operations. Table 5 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of
WE
or
CE
, whichever happens later. All data is latched on
the rising edge of
WE
or
CE
, whichever happens
first. Refer to the corresponding timing diagrams in the
AC Characteristics section.
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