參數(shù)資料
型號： F25L008A-100DG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 1M X 8 FLASH 3V PROM, PDIP8
封裝： 0.300 INCH, LEAD FREE, PLASTIC, DIP-8
文件頁數(shù)： 9/31頁
文件大?。?/td> 374K
代理商： F25L008A-100DG
ES MT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L008A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low transition of CE . Inputs will be accepted on the rising edge
F25L008A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.4
9/31
Publication Date
:
May. 2007
of SCK starting with the most significant bit. CE must be driven
TABLE 5: DEVICE OPERATION
INSTRUCTIONS
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Bus Cycle
3
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
2
4
5
6
S
OUT
Cycle Type/
Operation
1,2
Max
Freq
S
IN
03H
0BH
20H
D8H
60H
C7H
02H
S
OUT
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
S
IN
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
S
IN
S
IN
S
OUT
S
IN
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
S
OUT
D
OUT
X
-
-
S
IN
X
Read
High-Speed-Read
Sector-Erase
(4K Byte)
Block-Erase (64K Byte)
Chip-Erase
6
Byte-Program
5
Auto-Address-Increment-wor
d programming (AAI)
Read-Status-Register
(
RDSR
)
Enable-Write-Status-Registe
r
(
EWSR
)
8
Write-Status-Register
(
WRSR
)
8
Write-Enable (
WREN
)
11
33
MHz
A
15
-A
8
A
15
-A
8
A
15
-A
8
A
15
-A
8
X
X
-
-
D
OUT
Hi-Z
-
-
-
-
-
-
-
-
Hi-Z A
23
-A
16
Hi-Z
A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z D
IN
Hi-Z
ADH
Hi-Z A
23
-A
16
Hi-Z
A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z D
IN
0
Hi-Z
D
IN
1
Hi-Z
05H
Hi-Z
X
D
OUT
-
Note
7
-
Note
7
-
Note
7
50H
Hi-Z
-
-
-
-
-
-
-
-
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
06H
Hi-Z
-
-
-
-
-
-
-
-
Write-Disable (
WRDI
)
Read-Electronic-Signature
(
RES
)
Jedec-Read-ID (
JEDEC-ID
)
10
04H
Hi-Z
-
ABH
Hi-Z
X
13H
-
-
-
-
-
-
20H(Top)
21H(Bottom)
9FH
Hi-Z
X
8CH
X
X
14H
-
-
90H
(A0=0)
90H
(A0=1)
8CH
13H
13H
8CH
Read-ID (
RDID
)
Hi-Z A
23
-A
16
Hi-Z
A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z
X
X
Enable SO to output RY/BY#
Status during AAI (
EBSY
)
Disable
SO
RY/BY#
Status during AAI (
DBSY
)
70H
Hi-Z
-
-
-
-
-
-
-
-
to
output
50
MHz
100
MHz
80H
Hi-Z
-
-
-
-
-
-
-
-
1. Operation: S
IN
= Serial In, S
OUT
= Serial Out
2. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be V
IL
or V
IH
5. Prior to any Byte-Program, Sector-Erase , Block-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
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