參數資料
型號: F25L008A-100DG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 1M X 8 FLASH 3V PROM, PDIP8
封裝: 0.300 INCH, LEAD FREE, PLASTIC, DIP-8
文件頁數: 5/31頁
文件大小: 374K
代理商: F25L008A-100DG
ES MT
2
F25L008A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.4
5/31
Publication Date
:
May. 2007
47
:
32
31
:
16
15
:
0
4KB
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
:
4KB
4KB
0
0
1
0
:
1
4KB
4KB
0
0
0
1
:
0
4KB
0
0
0
0
Table2 : F25L008A Block Protection Table
TOP
Status Register Bit
BP2
BP1
0
0
0
0
1
1
1
1
Protected Memory Area
Address Range
None
Block 15
Block 14~15
Block 12~15
Block 8~15
Block 0~15
Block 0~15
Block 0~15
Protection Level
BP0
0
1
0
1
0
1
0
1
Block Range
0
0
0
1
1
0
0
1
1
None
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
F0000H – FFFFFH
E0000H – FFFFFH
C0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
BOTTOM
Status Register Bit
BP2
BP1
0
0
0
0
1
1
1
1
Protected Memory Area
Address Range
None
Block 0
Block 0~1
Block 0~3
Block 0~7
Block 0~15
Block 0~15
Block 0~15
Protection Level
BP0
0
1
0
1
0
1
0
1
Block Range
0
0
0
1
1
0
0
1
1
None
Bottom 1/16
Bottom 1/8
Bottom 1/4
Bottom 1/2
All Blocks
All Blocks
All Blocks
00000H – 0FFFFH
00000H – 1FFFFH
00000H – 3FFFFH
00000H – 7FFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
WP
is high or the
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
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