參數(shù)資料
型號： EVAL-ADUC831QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/76頁
文件大小： 0K
描述： KIT DEV FOR ADUC831 QUICK START
產(chǎn)品培訓(xùn)模塊： Process Control
標準包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC831
所含物品： 評估板、電源、纜線、軟件和說明文檔
產(chǎn)品目錄頁面： 739 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP
ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP
其它名稱： EVAL-ADUC831QS
EVAL-ADUC831QS-ND
REV. 0
ADuC831
–31–
ADuC831 Configuration SFR (CFG831)
The CFG831 SFR contains the necessary bits to configure the
internal XRAM, EPROM controller, PWM output selection
and frequency, DAC buffer, and the extended SP. By default it
configures the user into 8051 mode, i.e., extended SP is disabled,
internal XRAM is disabled.
CFG831
ADuC831 Config SFR
SFR Address
AFH
Power-On Default Value
10
*H
Bit Addressable
No
Table VIII. CFG831 SFR Bit Designations
Bit
Name
Description
7
EXSP
Extended SP Enable.
When set to “1” by the user, the stack will rollover from SPH/SP = 00FFH to 0100H.
When set to “0” by the user, the stack will roll over from SP = FFH to SP = 00H.
6
PWPO
PWM Pin Out Selection.
Set to “1” by the user = PWM output pins selected as P3.4 and P3.3.
Set to “0” by the user = PWM output pins selected as P2.6 and P2.7.
5
DBUF
DAC Output Buffer.
Set to “1” by the user = DAC. Output Buffer Bypassed.
Set to “0” by the user = DAC Output Buffer Enabled.
4
EPM2
Flash/EE Controller and PWM Clock Frequency Configuration Bits.
3
EPM1
Frequency should be configured such that Fosc/Divide Factor = 32 kHz + 50%.
2
EPM0
EPM2 EPM1 EPM0
Divide Factor
00
0
32
00
1
64
01
0
128
01
1
256
10
0
512
10
1
1024
1
RSVD
Reserved. This bit should always contain 0.
0
XRAMEN
XRAM Enable Bit.
When set to “1” the internal XRAM will be mapped into the lower 2 kBytes of the external address space.
When set to “0” the internal XRAM will not be accessible and the external data memory will be mapped
into the lower 2 kBytes of external data memory.
*Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their
correct values depending on the crystal frequency at power-up. The user should
not modify these bits so all instructions to the CFG831 register should use the
ORL, XRL, or ANL instructions. Value of 10H is for a 11.0592 MHz crystal.
相關(guān)PDF資料
PDF描述
HMM08DRKI CONN EDGECARD 16POS DIP .156 SLD
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