參數(shù)資料
型號： EVAL-AD7939CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/36頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7939CBZ
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： ±VREF
在以下條件下的電源（標準）： 13.5mW @ 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7939
已供物品： 板，CD
相關產品： AD7939BSUZ-ND - IC ADC 10BIT 8CH PARALL 32TQFP
AD7939BCPZ-ND - IC ADC 10BIT 8CH PARALL 32LFCSP
AD7939BCPZ-REEL7-ND - IC ADC 10BIT 8CH PARALL 32LFCSP
AD7939BSUZ-REEL7-ND - IC ADC 10BIT 8CH PARALL 32TQFP
AD7938/AD7939
Data Sheet
Rev. C | Page 18 of 36
CIRCUIT INFORMATION
The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit,
single-supply, successive approximation analog-to-digital
converters. The parts can operate from a 2.7 V to 5.25 V
power supply and feature throughput rates up to 1.5 MSPS.
The AD7938/AD7939 provide the user with an on-chip track-
and-hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP or
TQFP package.
The AD7938/AD7939 have eight analog input channels that
can be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo differential pairs, or seven pseudo
differential inputs with respect to one common input. There is
an on-chip user-programmable channel sequencer that allows
the user to select a sequence of channels through which the
ADC can progress and cycle with each consecutive falling edge
of CONVST.
The analog input range for the AD7938/AD7939 is 0 V to VREF
or 0 V to 2 × VREF, depending on the status of the RANGE bit in
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938/AD7939 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0, in
the control register.
CONVERTER OPERATION
The AD7938/AD7939 are successive approximation ADCs
based around two capacitive digital-to-analog converters
(DACs). Figure 15 and Figure 16 show simplified schematics of
the ADC in acquisition and conversion phase, respectively. The
ADC comprises control logic, an SAR, and two capacitive DACs.
Both figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
VIN is internally tied to AGND. In acquisition phase, SW3 is
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
03715-
023
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
Figure 15. ADC Acquisition Phase
When the ADC starts a conversion (Figure 16), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
03715-
024
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7938/AD7939 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code
transitions occur at successive LSB values (1 LSB, 2 LSBs, and
so on) and the LSB size is VREF/4,096 for the AD7938 and
VREF/1,024 for the AD7939. The ideal transfer characteristics
of the AD7938/AD7939 for both straight binary and twos
complement output coding are shown in Figure 17 and Figure 18,
respectively.
03715-
025
000...000
111...111
1 LSB = VREF/4096 (AD7938)
1 LSB = VREF/1024 (AD7939)
1 LSB
+VREF – 1 LSB
ANALOG INPUT
ADC
CO
DE
0V
NOTES
1. VREF IS EITHER VREF OR 2 × VREF.
000...001
000...010
111...110
111...000
011...111
Figure 17. AD7938/AD7939 Ideal Transfer Characteristic
with Straight Binary Output Coding
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