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參數(shù)資料
| 型號(hào)： | EVAL-AD7843EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/21頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7843 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.25 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 1.4mW @ 125kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7843 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7843ARUZ-ND - IC ADC 12BIT TOUCHSCREEN 16TSSOP AD7843ARUZ-REEL7-ND - IC ADC 12BIT TOUCHSCREEN 16TSSOP AD7843ARQZ-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP AD7843ARQZ-REEL7-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP AD7843ARQZ-REEL-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP |
AD7843
Rev. B | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02144-B
-003
1
2
3
4
5
6
7
10
8
9
11
12
13
14
15
16
AD7843
TOP VIEW
(Not to Scale)
+VCC
X+
Y+
X–
Y–
GND
IN3
IN4
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
+VCC
VREF
Figure 3. Pin Configuration QSOP/TSSOP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Function
1, 10
+VCC
Power Supply Input. The +VCC range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should be connected
directly together.
2
X+
X+ Position Input. ADC Input Channel 1.
3
Y+
Y+ Position Input. ADC Input Channel 2.
4
X
X Position Input.
5
Y
Y Position Input.
6
GND
Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and any external
reference signal should be referred to this GND voltage.
7
IN3
Auxiliary Input 1. ADC Input Channel 3.
8
IN4
Auxiliary Input 2. ADC Input Channel 4.
9
VREF
Reference Input for the AD7843. An external reference must be applied to this input. The voltage range for the
external reference is 1.0 V to +VCC. For specified performance, it is 2.5 V.
11
PENIRQ
Pen Interrupt. CMOS logic open-drain output (requires 10 k to 100 k pull-up register externally).
12
DOUT
Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high.
13
BUSY
BUSY Output. Logic Output. This output is high impedance when CS is high.
14
DIN
Data In. Logic input. Data to be written to the AD7843 control register is provided on this input and is clocked into
the register on the rising edge of DCLK (see the Control Register section).
15
CS
Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating conversions on the
AD7843 and also enables the serial input/output register.
16
DCLK
External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part. This clock input
is also used as the clock source for the AD7843 conversion process.
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