參數(shù)資料
型號(hào)： EVAL-AD7734EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/32頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7734
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 85mW @ 5V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7734
已供物品： 板，纜線，CD
產(chǎn)品目錄頁面： 779 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD7734BRUZ-REEL7TR-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP
AD7734BRUZ-REEL-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP
AD7734BRUZ-ND - IC ADC 24BIT 4-CH 28-TSSOP
AD7734BRU-ND - IC ADC 24BIT 4-CH 28-TSSOP
Data Sheet
AD7734
Rev. A | Page 5 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Power Dissipation (Normal Mode) 13
85
100
mW
AV
DD+DVDD Current (Standby Mode)
100
A
Power Dissipation (Standby Mode) 14
525
W
1 Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.
3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
5 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.
6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.
7 The adjacent channels are not affected by AIN voltage up to ±16.5 V.
8 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 k + 15.5 k = 124 k.
9 For specified performance. Part is functional with lower V
REF.
10 Dynamic current charging the sigma-delta modulator input switching capacitor.
11 Outside the specified calibration range, calibration is possible but the performance may degrade.
12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register).
14 External MCLKIN = 0 V or DV
DD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.
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